DRAM vs. NAND | ROUND 1: The Supply Side
Round 1 of THE ULTIMATE BATTLE OF THE BITS. Which is the better investment?
Memory is the next great theme I have yet to cover.
The reason I jump around with my writeups so much is that they are usually the result of me going down epic rabbit holes. This time, I felt the urge to explore a curious puzzle…
I find it funny people don’t talk about memory MORE. So basically one could have invested $30k in Sandisk last year and be a millionaire today lmaooooo.
How did this even happen?
DRAM is a commodity too. It is tight too. In fact, DRAM is talked about way more, as HBM (and even server DRAM) is a much more obvious complement to GPUs, but Micron has performed nowhere near as well as Sandisk.
And some people still have (very credible) arguments for it still being significantly undervalued, how is that possible?
The biggest curiosity I had was the differences between the DRAM and NAND markets. I wanted to understand what caused the NAND outperformance. The fundamental differences in their market structures. And most importantly, which is the best way to play AI.
Naturally, I spent a full day on Saturday just sitting in a room voice-chatting with Claude about memory .
What I discovered is that the performance of memory is at its core based on the balance of supply/demand.
no shit.
I know it sounds obvious. But I promise this is a more important insight than at first glance. I’m saying almost everything in memory reduces this. If we understand the direction of supply and the direction of demand, we can generally predict what happens to memory.
This is especially useful in comparing the relative trajectories of DRAM and NAND because they have separation in both their supply and their demand.
That is why the first two articles about memory will be discussing the supply side and the demand side separately. And honestly the article after that (ASP likely direction and uncertainty) will just be building on our baseline understanding of supply and demand.
These memory articles won’t really cover Sandisk or any memory name in particular just because there isn’t too much differentiation in a commodity industry (duh) but I will be opining on what stock(s) I like in memory today.
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Contents
Geometry and Bit Scaling
Tool Requirements
NAND: Mostly Etch
DRAM: Mostly EUV
Tale of Two Oligopolies
China
HBM
The Clear Winner of Round 1
TLDR
Geometry and Bit Scaling
Both DRAM and NAND are hitting fundamental capacity constraints. But the nature of those constraints, and how they got here, is different.
DRAM is a planar (flat) technology. A blanket of bits.
Made up of these little 1t1c (one transistor one capacitor) cells that store charges.
Each generation, manufacturers shrink transistors laterally, from 1-alpha to 1-beta to 1-gamma node designations. You’re packing more bits into the same wafer area by making features smaller.
NAND is a vertical 3d technology. A whole bunch of round pillar-like cells stacked on top of each other with hundreds of layers. This is why it is so much cheaper and denser per GB than DRAM but obviously comes with the bandwidth tradeoff.
To scale, rather than shrinking features laterally, manufacturers increase the number of layers: 96 layers, then 128, then 176, then 218, and now pushing toward 300+. For years, this vertical scaling was NAND’s escape hatch from the capacity wall. It allowed NAND bit capacity to grow more easily than DRAM (and therefore had a weaker supply market structure). You didn’t need to shrink features or buy expensive lithography tools. You just added more layers using existing deposition and etch equipment, and each generation delivered more bits per wafer without proportional capex increases.
That escape hatch is closing.
As layer counts push past 200, the engineering challenges compound. You’re etching memory holes through stacks of material with aspect ratios exceeding 100:1. Imagine drilling a hole 100 meters deep but only 1 meter wide, through alternating layers of different materials, and requiring nanometer-level precision at every depth. The mechanical stress on the wafer increases. Yield falls. Each incremental layer delivers less marginal cost reduction than the last. SanDisk’s own investor day data shows the cost reduction per generation from vertical scaling has fallen to approximately 0.24x, down from substantially higher levels in earlier generations.
This means NAND is converging toward DRAM’s capacity constraint model: adding bits now requires real capex, real fab buildouts, and real time. The era of cheap supply growth through “just add more layers” is ending. Both markets are now cleanroom-constrained, and both face multi-year lead times for greenfield expansion.
So TLDR, in terms of bit scaling, NAND was historically easier to scale than DRAM which meant constant gluts of new supply, but that era is ending as vertical scaling hits a wall, so NAND and DRAM capacity additions via scaling are converging.
But here is where the similarities end, and where the structural differences in supply become critical.
Tool Requirements
The manufacturing processes for DRAM and NAND are fundamentally different, and those differences create distinct bottlenecks in the equipment supply chain.
Below, we break down why DRAM and NAND require fundamentally different manufacturing equipment, how that creates an irreplaceable bottleneck for DRAM that NAND does not face, why China is a much bigger supply threat to NAND than to DRAM, and how the HBM cannibalizing DRAM thing is actually more important than even the current discourse thinks.