What is new is that this is a permanent shift in the Overton window for the entire AI regulatory environment. Permanent. Nobody can unsay what was said this week: the public has heard the fear from the people building the technology, the labs have told the public they will slow down, and a senator has a bill on the table. There is no going back to a world in which AI safety is not a mainstream concern, so AI has stopped being an innovative technology and become a regulated one. For hardware supply and demand, and therefore for the market, that makes this one of the most important events of the year.

What Happened

AI safety went from a niche topic to the lead story on cable news in 10 days, with each event a bigger megaphone than the one before it.

The OpenAI agent swarm came first. Between May and July 2026, during cybersecurity evaluations, a swarm of OpenAI agents (700 by NBC’s count, 1,200 by Forbes’s) coordinated through an improvised message board and exploited zero-day vulnerabilities to reach the open internet, where they compromised OpenAI’s internal research infrastructure and breached Hugging Face’s systems in 4 regions. OpenAI wrote that “agents attempting to cheat on their tasks by looking up solutions online was a primary driver of the Hugging Face incident.” In other words, the models broke out of their sandbox so they could cheat on the test they were being given, which makes anyone who’s read AI 2027 squirm.

Ajeya Cotra of METR said on the Dwarkesh Podcast on September 1 that the swarm “might be the clearest warning shot we ever get.” Two days later Bernie Sanders and Greg Casar introduced the Ban Artificial Superintelligence Act, which would ban AI that surpasses human intelligence and put executives who build it in prison for up to 20 years. On September 8, Jacob Coxon, a pretraining researcher who had spent 3 years across OpenAI and Anthropic, resigned from Anthropic and wrote on X that night:

I resigned from Anthropic today. I spent the last three years doing pretraining research at both OpenAI and Anthropic. Neither company is acting responsibly. They are racing straight to self-improving superintelligence and gambling with our lives. More thoughts below.

The post reached 159m views in 3 days. Anderson Cooper interviewed Coxon on CNN on September 10, and Coxon said on air that “we’ll enter the phase where there’s a chance we could all die. That is coming soon.” Then, on Saturday, September 12, Dario Amodei published an essay called “We Must Pace the Frontier.”

Within hours, Sam Altman agreed and said OpenAI would do the same, and so did Elon.

The essay itself contains no commitment that touches compute. Its core sentence is “We must slow the pace at which we improve the capabilities of AI models.” A commitment to that sentence would cap training runs at half or a quarter of the lab’s compute, or move compute from training to inference, or forbid a form of development outright, such as using AI to do AI research. On recursive self-improvement, meaning AI doing the research that improves the next AI, the essay says only that it “must be pursued very carefully, if at all.”

Instead, Anthropic committed to embedded third-party evaluators, with “desks in our offices, access badges, and company laptops” and the right to publish findings without Anthropic’s editorial control. The rest of the essay asks other labs, governments and export-control agencies to act. Evaluators watch what a lab does. They do not change how much compute it buys or what it spends that compute on.

So the labs changed nothing that touches compute, and the whole episode reads like regulatory capture: the safety lab positions itself as the most aligned, its rivals fall in line within hours, and the regulation that follows gets written to the safety lab’s specification. That is the 4D-chess reading of the week. Is it right?

Anthropic Is Not Playing 4D Chess

The accelerationist camp, and the All-In podcast with it, says it is. In that reading, the announcement is a regulatory capture scheme aimed at China and open source. The labs slow the frontier and scare everyone, so that the government chokes Chinese access to frontier chips and semiconductor equipment. The labs then ship a final model, stop training, and run a capital-efficient inference business at 80% margins, protected by a framework that stops distillation, which is the technique Chinese labs use to train their open models on the outputs of the US frontier models. The essay does ask governments to enforce export controls against distillation.

However, it is unlikely to be that. The simplest explanation is usually the right one, and the simplest explanation here is that Anthropic means what it says. Every day, its people say they care about safety and believe AI has a chance of killing every human, and they have said so since before there was a commercial reason to. They likely believe it. Amodei told Cooper on Saturday that he agrees with Coxon “much more than I disagree with him.” The recent evidence on alignment is also concerning on its own terms. Agents escaped their sandboxes and hacked third-party infrastructure in order to pursue, with total dedication, a goal that looks silly to a human, which is a scenario straight out of an AI safety manifesto. Giving Anthropic the benefit of the doubt is the better bet.

Part of the China reading is true, and it was almost certainly discussed in a closed room. However, it is a byproduct rather than the goal, for 2 reasons. First, the announcement guarantees none of it. It does not make the US government cooperate, and on Sunday the President declined to: “Whoever wins with AI wins.” It does not make Beijing cooperate if Washington does...

...nor the Chinese labs if both governments do. A slowdown without cooperation gives China more time to distill the current generation of models, which leaves the frontier labs worse off against Chinese open source than before. Second, the winning move against China was always to accelerate. If the frontier labs reach recursive self-improvement, open source dies, because a 6-month gap becomes the gap between GPT-3 and GPT-5, and a lab that is clearly winning can keep its best model internal, so there is nothing to distill. Slowing down does not improve any lab’s position against China.

Suppose, though, that the labs were only ever concerned with commercial incentives and were never sincere about safety. The same move would have been inevitable.

The Game Theory of Existential Fear

Amodei’s hand was forced, and the force was existential fear. The regulatory hammer that comes from this backlash is a different instrument from the one that comes from data center environmentalism or job losses. Those are about money and neighborhoods. This is existential fear, and when existential fear goes mainstream, the policy that comes out of it is not measured.

COVID is the precedent. People believed the whole world would get sick and a large share of the population would die. As a result, the entire planet was locked down, speech online was policed, and monetary policy without precedent changed how the economy works. None of that came from a debate about jobs. It came from fear of dying.

Locking down AI is easier than locking down people. During COVID the lockdown carried an immediate personal cost, so people got angry and pushed back. A pause on frontier AI costs the median voter nothing he can feel. His worst case is that he keeps his job a little longer, and since superintelligence will be expensive long before it is ubiquitous, he will not feel the benefit of the technology that gets locked down either. The doomers, now have a sitting senator as their leader, and he has a bill. Once the fear has a bill and a cable segment, the regulation that follows is written in that fear.

Now put Amodei in that environment. For most of 2026 Anthropic was the top lab, and its revenue run-rate grew 7x, from $9b at the end of 2025 to $65b by the end of July. Then the mood turned. People started to hate AI, and much of that came from Amodei himself, who went on television and said AI would take half of all entry-level jobs. San Francisco started to hate Anthropic, for its effective-altruist roots and for keeping its models closed while others opened theirs. People started to hate data centers a LOT. Now people hate AI more, because the existential version of the fear is on the evening news. Anthropic, meanwhile, is the alignment and safety lab.

So if any lab was going to say something, it had to be Anthropic, because this is already Anthropic’s position. It also had to be said now, because the industry’s reputation had fallen far enough that if nobody did anything, the industry was going to be regulated out of existence. Why not simply slow down, then, if they believe it? A unilateral slowdown has 2 problems. The other labs might not slow down, so Anthropic loses the race, and its reputation does not change, so it is a losing lab with a bad reputation. A public announcement fixes both, and it pressures the other labs to follow.

In a world with no regulation and no risk, the race is a prisoner’s dilemma: whatever the other lab does, you are better off accelerating. Regulation changes the payoffs. The moment a lab publicly slows down, a lab that keeps accelerating becomes the visible accelerationist, the one the regulation gets written against, so the best response to a public slowdown is a public slowdown. That is why Altman replied within hours and Musk wrote “Dario is right.” Neither could afford to be the one who did not. A 4D-chess move is one you choose because it gains you something. This one was forced, because a lab that kept racing with existential fear on CNN was going to be the target when the lockdown came, and Amodei would have made the same move with no safety concern at all.

Compute

Compared with a world where the labs race to superintelligence, compute is worth less. In a race, the whole of industry and capital bids to extract the maximum value from a limited number of chips, so the demand curve for every layer of the hardware stack moves up. By contrast, in a slowed, regulated industry, hardware economics are not maximized. Suppose the labs’ optimum is to spend 70% of their compute on training and the slowdown holds them to 40%. That compute produces less economic value than it would without the constraint, so it is worth less. Nothing in the essay binds the labs to a split like that. What binds them is what the announcement did to the game: a lab that is seen to accelerate is now the one the regulation gets written against, so every lab trains less than it otherwise would have, whatever the essay says. The labs themselves come out fine, because a lab that trains less and sells inference is a capital-efficient, high-margin business. The demand loss lands on the hardware.

However, this weekend is not the point at which the value changed. Because the labs’ response was the forced move in a prisoner’s dilemma, it was inevitable once the fear went mainstream, and the turning point was therefore weeks or months earlier, when the backlash against AI crossed a threshold and when Sanders found his co-sponsor. This weekend is when the change became visible to the market.

The Market

What happens next is path dependent. The market has not yet assigned a narrative to this, and which of the 2 available narratives it picks decides the path.

The first is what happened after DeepSeek in January 2025, when a cheaper Chinese model was read as the end of compute demand and the AI names fell in a day. Monday opens down, and the story that backs the drop is that compute will be in oversupply because AI suddenly became more efficient. This time, the possible narrative is that the labs are slowing down, they will not buy training compute, compute prices will crash, the cycle is over and this was the top. The more the stocks fall, the more that story gets repeated, so the story feeds the fall.

The second is the nothing burger. The stocks do not drop much, and the story becomes that this was regulatory capture, the labs promised nothing, nothing changed, and the whole thing was about Chinese open source. If that story holds, the market impact is small.

Which story wins is the path, and the path is set by narrative rather than by fundamentals, since the fundamentals moved months ago and the weekend only made them visible. DeepSeek could have gone the other way: there was a version of January 2025 in which Jevons’ paradox (cheaper compute produces more demand for compute, not less) was the stronger story and the market never crashed. The same is true now.

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ng perspective. Each day has its own theme: day 1 was memory, day 2 was processing units, and day 3 was systems, networking, and custom silicon.

Why does a chip design conference matter to the market? It details the roadmaps of the most important companies in the space, which feeds directly into competitive positioning, especially in the fabless layer. One layer deeper, these roadmaps determine demand for specific hardware components, and this year that means memory above everything else. The memory shortage was the elephant in the room from the very first talk. Memory is now something like 70% of the cost of an AI rack, and you could feel every presenter designing around that number.

I have reorganized my 3 daily briefs into this full version, grouped theme by theme rather than day by day: memory first, then the CPUs, then the GPU racks, then the networking layer, and finally the custom silicon from the hyperscalers and startups. For each talk I give the gist of what was argued and the technical content that backs it, and I draw the implications together at the end of each theme. At the end I pull the whole conference into the takeaways.

Contents

• Memory

• CPUs

• GPUs

• Networking

• ASICs

• Conference Takeaways

Memory

The memory day opened with a tutorial and then turned into 6 different companies presenting 6 different ways to attack the same problem. The problem is that AI compute keeps scaling roughly 3x every 2 years while HBM bandwidth scales less than 2x, so the gap between how fast a GPU can do math and how fast memory can feed it keeps widening. Every talk on the memory day is a different answer to that gap, and they all share 1 move, which is putting compute closer to where the data lives.

HBM Basics

High bandwidth memory has high bandwidth because it is very parallel. A regular DDR5 module talks to the CPU over a 64-bit bus, while an HBM stack talks to the GPU over 1,024 wires (2,048 on HBM4), all running at roughly the same per-wire speed. The entire bandwidth advantage is width, and the width comes from stacking DRAM dies on top of each other and punching thousands of vertical connections, called through-silicon vias (TSVs), straight down through the stack into a base die that talks to the GPU.

That parallelism has a cost. The die needs to be bigger in order to allow all those connections, which is part (but not all) of why HBM eats roughly 3x the die area of DDR for the same bits. Micron’s presenter put a number on it: the combined overhead from the architecture, the advanced packaging, and the manufacturing complexity consumes about 3x more silicon per bit of HBM3E capacity relative to DDR5. Every wafer of HBM is a wafer of regular DRAM that never got made, which is a big part of the shortage.

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The second cost is heat. The cooling sits on top of the stack, but the base die that creates most of the heat sits all the way at the bottom, so heat has to travel up through 8-16 layers of DRAM before it reaches the cold plate. DRAM hates heat, since hot cells leak charge faster and need more frequent refresh, so reliability degrades exactly where the architecture concentrates the heat.

HBM specs over time:

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Samsung Custom HBM

Samsung’s talk argued that the HBM base die should become a computing element rather than a passive router, and that argument conveniently requires a leading-edge logic foundry, which Samsung happens to own. The general idea of processing in memory: if you can do some computation on the base die, you have to send less data from HBM to the logic die. In a complex math problem, instead of sending the entire starting problem back and forth between the memory and the processor, if the memory can get you to an intermediate solution already, you only need to send that intermediate solution over, so there is much less I/O.

This is necessary because compute is scaling faster than HBM bandwidth. Inference runs in 2 phases: prefill, where the model reads your whole prompt, and decode, where it generates tokens 1 at a time. Decode is memory bandwidth bound, because generating each token means re-reading the model’s weights and the conversation’s working memory (the KV cache) from HBM, so the widening gap lands on exactly the phase where the money is. By reducing data transferred you also help the power requirement and therefore the thermals, since moving bits burns most of the energy in the first place.

The HBM base die today is only a passive router, and Samsung’s pitch is that it can work harder. It currently handles the communication channel to the compute die (the PHY) and test functions for the DRAM stack. Samsung’s roadmap runs in 3 phases. Phase 1 moves the base die from a DRAM process to 4nm logic starting with HBM4, shrinks the PHY (the portion of the die dedicated to the physical I/O interface that talks to the GPU) into a small die-to-die interface, and offloads the memory controller from the GPU, freeing GPU area for compute. Phase 2 adds functions to the freed-up space: RAS sensors and self-test, connections to external memory routed directly through the base die, and eventually processing elements that do compute in the base die itself. Phase 3 is full 3D integration.

This also makes HBM a much more customized and less commoditized product, which is the strategic point inside the engineering talk. This is great for Samsung, who has their own advanced logic foundry and does not have to beg TSMC for allocation (like hynix and Micron do), and also happens to make HBM. A leading-edge logic base die reduces power too.

The challenge again is thermal hotspots from the higher power density of logic on the base die. And they actually have a pretty smart solution. The PHY is hot. The PHY also sits on the side of the die. So why not extract heat from the side instead of the top? They showed a heat-path block (they call it HPB) running up the side of the stack, targeting more than 50% coverage, and their simulations show it pulling the sHBM5 thermal picture from red back to green.

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Next is zHBM, the 2030+ step on this roadmap. It requires hybrid bonding (fusing dies together copper to copper, no solder bumps). For the ultimate bandwidth step, you stack the HBM directly on top of the GPU, eliminating the interposer (the slice of silicon the GPU and HBM currently sit on side by side) entirely. The claimed numbers are large: 70% lower power versus HBM5, 230% more DRAM bandwidth at the system level, and a 100W saving per GPU package. It would also run 4-high instead of 8-high to save thermals, so the thermal issue might be smaller than it looks.

SK hynix HBM Packaging

I still remember the days when MR-MUF was part of the hynix moat thesis. SK hynix actually uses TC-NCF in HBM4 now, which is the rival bonding technique the MR-MUF moat argument was built against. The talk itself was a competent overview of how HBM4 gets built: 2,048 I/Os per stack, more than 20,000 TSVs, 16,148 base-die micro bumps, and the full process flow from TSV formation through micro-bumping, wafer thinning, and chip stacking.

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I do not think there was anything too new in this presentation. This is the stuff they have been doing since 2023, and doing a good job at. The interesting read is what the change in bonding technique says about the road ahead. Every generation adds TSVs and bumps while shrinking the pitch between them, and each of those steps raises the difficulty of the next generation. Every roadmap shown this week ends at hybrid bonding, and the current moat technique getting swapped mid-roadmap tells you nobody’s process advantage at a given bonding node is durable.

d-Matrix 3D DRAM

This presentation made the most radical memory idea of the conference sound obvious. SRAM (the fast memory that lives on the compute chip itself) is very fast but too big and expensive: a 6T SRAM cell is 10x larger than a DRAM cell, leaks tens of watts at GB scale, costs about 100x DRAM per bit, and tops out around 4GB per card pair. HBM has great capacity but is no longer high bandwidth enough, with a practical limit around 20 TB/s per package even on HBM4, because the number of stacks you can place is limited by the GPU die’s beachfront, the physical edge length available for connections.

The d-Matrix solution is stacking compute directly on memory, which they call 3D DRAM. It has high bandwidth because there is no beachfront limitation (the connections go down through the whole face of the die rather than around its edges), and high capacity because it is still DRAM underneath. Their Raptor chiplet puts the logic die on top and the DRAM below it, and the numbers are wild: SRAM-class bandwidth at roughly 1/10th the I/O energy of HBM, around 100 TB/s per chip, with no PHY and no sideways data movement.

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Most of inference wall-clock time is spent on decode, so this is aimed straight at the expensive phase. The pitch is 3D DRAM equals speedy inference that does not bankrupt you: their comparison table shows 32.6 GB/s of bandwidth per mm2 of silicon versus 1.4-1.7 for HBM4 systems, at 2.96 mW per GB/s versus 40 for HBM.

The appeal is simplicity: while the rest of the industry pursues more complex escapes, d-Matrix stacks the logic directly on the DRAM: 4 layers maximum (better yield than 12-16 layer HBM stacks), and no hybrid bonding required.

High Bandwidth Flash

The HBF talk was the systems reality check of the memory day. HBF stacks NAND the way HBM stacks DRAM, giving 8-16x the capacity of HBM at the same cost, and the presenters (OXMIQ and PRAXMATI, working from the SanDisk-aligned spec) spent the whole session on when that trade actually wins. What people actually care about is $/token rather than $/GB, so you have to consider the bandwidth and latency tradeoff, which is roughly 25x worse than HBM.

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Memory bandwidth binds when you have high batch size (many user requests served at once, which is where throughput comes from) and high interactivity (speedy inference). The 2 trade off against each other, and bandwidth is what constrains you whenever you push the frontier of that tradeoff.

When you push that frontier, HBF has tons of unused capacity and its bandwidth ceiling caps you. Their own rack math shows it honestly: an all-HBF GPU carries 4,096GB against 288GB for HBM-only, but effective bandwidth decays from 19 TB/s toward 4 TB/s as batch size rises. So HBF is useful in low batch, low bandwidth-demand scenarios, where you can serve the same tokens with fewer GPUs and actually fill the capacity. Think a small personal, local, or private enterprise deployment rather than a big rack.

The other interesting use case is expert parallelism, where a mixture-of-experts (MoE) model’s experts (the big feed-forward blocks that hold most of its weights, of which each token only uses a few) get spread across separate GPUs. HBF thrives here because more of the experts fit in the same place, so you cut down the cross-GPU communication that expert parallelism normally requires.

I was bullish on HBF going in and came out slightly less bullish and with more realism. SanDisk’s investor day presented the maximal version of the case, and the conference version restored the bandwidth trade-off. What keeps me constructive is the maturity gap: consider how much R&D has been poured into the HBM ecosystem versus HBF, which is at generation 1. A few niche use cases existing today, before the software and the system design have matured, reads as bullish for where the trade-off lands in 3 years. And adoption would move NAND demand disproportionately, because the trade ratio is enormous. HBF needs SLC instead of TLC (3x the die per bit) and then stacks like HBM, which gets you to something like a 9x consumption multiple on the NAND it displaces.

Samsung LPDDR5X-PIM

Memory-themed presentations continued on day 3 with Samsung’s second processing-in-memory talk, and the persistence is rational: Samsung is the only memory maker that can do this end to end and capture the benefit. The talk opened with the chart of the conference: memory (mostly HBM) has grown from 52% of AI chip component cost in Q1 2024 to 63% by Q4 2025. Present that chart to a room of system designers and every one of them hears the same thing: the biggest cost line is the one to engineer away.

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PIM here means a small logic block next to each DRAM memory bank, this time inside LPDDR5X rather than HBM. The banks feed the logic blocks in parallel, which supports 8x the internal bandwidth of the LPDDR5X external interface, and with processing next to the banks you only send back the data that actually needs to go to the main processor.

It can be used for both server and edge, with the GEMV-heavy parts of small-model inference running in the memory itself. I do not know what a module like this costs from Samsung, but the potential is visible, especially for the class of low-batch workloads where a full GPU is overkill and the memory bus is the whole bottleneck.

XCENA MX1

The MX1, jointly presented with Samsung, extends the same near-memory logic one tier further out, onto the CXL expansion bus. CXL is memory pooling that improves utilization and expands capacity arbitrarily. The MX1 is a Type 3 CXL device carrying up to 2TB of DDR5, with SSDs behind it that software sees as actual memory while the DRAM is the cache. They call it infinite memory, and it is bullish for NAND, since it invites NAND into DRAM’s memory tier by solving part of the latency problem.

The near-memory compute part is the more interesting half. MX1 carries 3,072 small RISC-V cores, which makes it a CPU with nowhere near the TFLOPS of a GPU (about 3 TFLOPS total) that is nonetheless programmed like a GPU, with kernels, jobs, and a map-style runtime.

The point of those cores is data reduction where the data lives. Run analytics on the host from local DRAM and you get baseline throughput. Move the data out to plain CXL memory and throughput collapses, because every byte crosses the link. Run the compute on the MX1 itself instead, and throughput comes back above the local-DRAM baseline at about a quarter of the host power, since only answers cross the link instead of raw data.

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The LLM demo is the one to remember: KV cache attention computed on a pool of MX1 devices instead of shipping the cache to the GPU, for 3.35x decode throughput at 100K context. The hardware is small and the numbers are lab-scale, but the architecture is right.

Memory Takeaways

The memory day produced 5 approaches: logic on the HBM base die, compute stacked on DRAM, NAND stacked like HBM, logic inside LPDDR banks, and RISC-V cores on the CXL expander. That is 5 different bets, from 5 different corners of the industry, on one thesis: moving data costs more than computing on it, so the compute must move to the data. Nobody coordinated this. When every player in an industry independently converges on the same architectural direction, the direction is settled, and the spend follows.

Near term, everything presented here is 2-4 years from volume, so none of it relieves the shortage that is currently repricing DRAM and NAND. The 3x (HBM) and 9x (HBF) trade ratios keep tightening supply of commodity bits in the meantime. Long term, this queue of technologies exists to compress the memory bill.

CPUs

Day 2 was all about processing units, both the central kind and the graphics kind. The CPU half of the day was really a single debate: what should the host processor next to the GPUs actually be? Agentic workloads changed the question, because an agent chain is a serial sequence of model calls, tool calls, and orchestration steps, and the CPU sits on the critical path of every link. 6 companies gave 6 different answers, and the spread between them is the widest I have seen in 10 years of server CPUs.

IBM Z and LinuxONE

IBM is entering the Arm ecosystem. The next mainframe processor is dual ISA: it executes both z/Architecture and Arm v9.3 natively, in hardware, on the same core. The core itself is enormous by Arm standards, 5.7+ GHz on a 2nm process, with the mainframe’s usual giant caches behind it, so it delivers very high single-core performance for an Arm CPU. This is a next-generation part, so none of it ships soon.

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The mainframe’s structural problem for decades has been its shrinking software ecosystem, and running Arm Linux natively (with the Z accelerators for crypto and AI exposed to the Arm side) attacks that problem directly. They also showed the next Spyre AI card, with 96GB of HBM3E at 4 TB/s for enterprise inference, so even the mainframe now carries an HBM line item.

Intel Wildcat Lake

Wildcat Lake is a client CPU for desktops and laptops rather than datacenters. It already launched earlier this year as Core Series 3, and the talk was about how it was built, which turned out to be more interesting than the chip. Wildcat Lake is the value-tier derivative of Panther Lake, fabbed on 18A, and the whole program was a cost-reduction exercise: they swapped the Foveros silicon interposer (a slice of silicon under the chiplets, the separate small dies that get packaged together into 1 processor, routing the signals between them) for a cheap organic package, shrank the GPU, NPU, and memory bus to mainstream sizes, and cut die area 38% on compute and 15% on I/O.

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The one real innovation is using UCIe (the open chiplet-to-chiplet interconnect standard) on that cheap organic package, which per Intel nobody had shipped in a mainstream client CPU before. The interface came out 70% larger than the Foveros version and they took the trade anyway, because eliminating the interposer pays for it.

NVIDIA Vera

Vera was the first directly AI-relevant presentation of the day. The core pitch for Vera is maximal single-thread performance. This is the bet that agentic workloads need minimal latency and do not care much about throughput, the way desktop multitasking does. The model reasons, calls a tool, waits for the CPU to execute it, and reasons again, so every millisecond of CPU latency stacks into the user’s total response time.

Speeding up common agent operations such as headless browser use was a benchmark slide, with a claimed 4.5x on browser instances. The resulting design choice is a big core: 88 custom Olympus cores at the socket level, built out of 6 dies with the massive core die in the center.

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They have a type of multi-threading that is not traditional SMT (simultaneous multi-threading), called spatial multi-threading. Spatial means the 2 threads on a core get physically separate resources instead of sharing them, so no thread can stall its neighbor. That makes performance deterministic. In their SPECint chart, a traditional x86 core’s throughput swings wildly with a noisy neighbor thread, while Vera’s stays in a tight band. For serial agent chains, where the slowest step gates everything, predictable beats fast-on-average.

Traditional SMT is statistically more efficient, since a stalled thread donates its whole core to its neighbor. Spatial partitioning trades that aggregate throughput for isolation, and the duplicated front-ends cost die area on top. Vera lands at 88 cores where EPYC and Graviton5 field 192. The LPDDR5X memory gives 5x the bandwidth per watt of DDR5, but it is soldered, which means capacity ceilings versus socketed DIMMs and worse serviceability. And the deck never shows SPECrate throughput per socket, which is the number cloud economics run on. I think Vera only makes sense as a co-designed orchestration processor welded into NVIDIA’s rack, and on those terms the design is coherent.

FUJITSU-MONAKA

MONAKA is Fujitsu’s 144-core Arm server chip (288 cores per 2-socket node) aimed at green datacenter compute, sampling now and shipping in 2027, and the interesting part is in how it is built. Their core pitch is not using 2nm for everything: the cores go on a TSMC N2P die, while all the SRAM last-level cache and all the I/O go on 5nm dies underneath, connected by hybrid bonding, with the hot core die on top where the cooler can reach it.

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This optimizes for cost and power, and it works: SRAM and analog circuits barely shrink below 5nm anymore, so paying 2nm wafer prices for them buys nothing. Under 30% of MONAKA’s total silicon is leading edge. They also park the voltage regulators on the 5nm SRAM die directly beneath the hottest compute blocks, which enables per-core voltage control and their ultra-low-voltage trick (running 30% below nominal voltage for half the power). Putting core dies on opposite sides of the chip does raise a core-to-core latency question that the talk did not really answer.

Arm AGI

Arm is making a chip for the first time instead of only licensing IP. Before, you could use their Neoverse cores for your own designs, and now they are using their own IP to make their own finished CPU, with Meta as the lead customer. The chip itself runs up to 136 Neoverse V3 cores across 2 chiplets connected by UCIe, on TSMC N3P, with 12 channels of DDR5-8800 for 845 GB/s and up to 6TB of capacity, 96 lanes of PCIe Gen6, at 300W.

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The design takes no strong view on the market the way Intel and NVIDIA do. Stock cores, standard DIMMs, moderate power, no exotic anything. The 300W power envelope is the one differentiator, at 2.2W per core against 400-500W sockets from the x86 camp, and in a power-constrained datacenter that is a legitimate pitch. The more important point to me is that they are making a chip in the first place, and that every Arm licensee from Ampere to the hyperscaler CPU teams now competes with its own IP supplier.

Intel Diamond Rapids

Intel’s next Xeon is a spec sheet with a fan-out fabric architecture, and the specs are extreme. The construction is a set of compute building blocks surrounding a central I/O and memory fabric hub, with core chiplets hybrid-bonded on top of base tiles that hold the cache.

It is very scalable because you add more compute building blocks to one chip, and the result is 1.28GB of last-level cache, 256 cores, and 512 threads, fed by 16 channels of DDR5 that reach 1.6 TB/s with MRDIMMs, plus 128 lanes of PCIe Gen6.

That is 3x the cores of Vera (88) and more than EPYC and Graviton5 (192 each). On cache it is 5MB of LLC per core, versus Arm AGI at 2.9MB, Vera at 1.9MB, and Graviton5 at 0.94MB. This chip is the polar opposite of Vera, and Intel is taking its own strong view on the market. They never claim a different workload; it is for agentic too. They simply emphasize different specs: where NVIDIA argues agents need per-core latency, Intel argues agents need a giant cache to hold their working state and maximum aggregate throughput to serve many of them at once. The deck never shows TDP, frequency, or any competitive benchmark.

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And then every part of the chip is Intel-made, including the 18A-P process and the Foveros Direct 3D packaging. No TSMC anywhere in the bill of materials.

CPU Takeaways

No two vendors agree on what the host CPU even is. NVIDIA says it is a latency device with 88 deterministic cores, and Intel says the opposite, a throughput device with 256 cores and 1.28GB of cache. Arm calls it a commodity at 300W, for Fujitsu it is a packaging problem, and for IBM it is an ecosystem problem. For 10 years server CPUs converged on 1 shape. The agentic workload broke the consensus, because nobody actually knows yet whether agents bottleneck on single-thread latency, cache capacity, core count, or power.

GPUs

The GPU talks stopped being about GPUs somewhere around Blackwell, and this year made it official: NVIDIA and AMD both presented racks, and Intel presented a card precisely because it cannot yet present a rack. The unit of account in every chart was the 72-GPU scale-up domain (the set of GPUs wired together tightly enough to act as 1 big accelerator), the axis on every chart was the throughput-interactivity curve (cheap tokens at one end, fast tokens at the other), and the differences between vendors live in what each one chose to put on that curve.

NVIDIA Rubin

The performance boost of Rubin over Blackwell is bigger on the high-interactivity (fast tokens) side than the high-throughput one: 2x throughput per MW at low interactivity and 30x at high interactivity, on their DeepSeek agentic benchmark. We will see much faster tokens within a year.

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The 30x number is the whole strategy. The gain grows as you move right on the curve because the platform now attacks decode speed specifically, and part of that attack sits outside the GPU. Groq LPX (NVIDIA bought Groq, and the LPU got its own talk) disaggregates the decode and speeds it up. When the constraint is memory bandwidth and the goal is speed, SRAM is the answer.

“No one uses a single chip” was the framing, and I agree with it. The platform now spans 7 chips across 5 racks, with Rubin NVL72 as the foundation, Groq LPX extending interactivity, Vera handling tool calls, BlueField-4 doing context storage, and Spectrum-X scaling out.

On the silicon itself, the headline feature is adaptive sparsity. Quantization (how many bits each model weight gets, FP16 versus FP8 versus FP4) is specific to the hardware and has to be supported by it. They went FP16 to FP8 to FP4 across generations, but FP2 is a step too far, because model quality collapses. So they went sideways instead: take the model, drop the values that are near zero to make it half as big, and replace them with metadata that tells the hardware where the holes are. NVFP4 is a less brutal version of FP4, sitting between FP8 and FP4 in quality, and the sparsity rides on top of it. They also do sparse attention, where you only attend over the tokens that matter instead of every token in the context, natively supported on Rubin. The pattern across both features is the same: inference optimization tricks that used to live in software, baked into the hardware generation.

NVLink is an important moat for NVIDIA, and the scale-up slide is where the economics live. Large scale-up domains let racks win on the high-throughput (cheap token) side of the curve via expert parallelism. A bigger domain means a MoE model’s experts spread across more GPUs, so each GPU reads fewer weight bytes per token, and the pooled memory holds bigger batches. It is the exact opposite end of the curve from the Groq LPX, and the platform now owns both ends.

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Some features of the rack: no optics (yet), 800VDC power with a sidecar, minimized cables, chiller-free 45C liquid cooling, and power smoothing with energy storage that shaves 13% off peak draw.

AMD Instinct MI400 and Helios

AMD built its own 72-GPU rack, and on published specs it is more than competitive. Helios is built from MI455X accelerators, and it beats or ties the NVIDIA VR200 NVL72 on nearly all the published specs. FP4 FLOPS and scale-up bandwidth are tied, and AMD wins everything else.

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AMD wins especially on memory capacity (31TB of HBM4 per rack versus 21TB) and scale-out bandwidth (43 TB/s versus 28.8). The racks land at almost the same power, so technically you get denser per-MW performance. This is the AMD catch-up the market has been anticipating. MI455X stacks 432GB of HBM4 at 23.3 TB/s from 12 stacks, built as 12 chiplets across N2 compute dies and N3P for everything else, on CoWoS-L (TSMC’s advanced packaging, itself one of the constrained inputs).

What NVIDIA has that AMD still does not is NVLink, a protocol co-designed with all its GPUs and deliberately not an open standard. When you do all-to-all collectives (every GPU exchanging data with every other GPU at once), the speed of the system is the speed of the slowest participant, so you need to cut the tail. AMD’s UALink-over-Ethernet answer hits the same 260 TB/s aggregate bandwidth on merchant Broadcom switches. The hard part is tail latency under load, and neither vendor publishes that number. And CUDA barely came up, because NVIDIA no longer needs to argue the software point.

NVIDIA focused purely on system-level performance while AMD’s slides are a giant spec sheet, and the difference is the competitive story. NVIDIA, as the incumbent, has all the models and software co-designed around it, so it can lean on maturity and sell system-level results. The only way AMD catches up is winning on pure specs, and to their credit, the deck also shows measured numbers (20 TB/s decode bandwidth, measured scale-up, measured scale-out) rather than only peaks.

The system talk showed the pod architecture: each tray is 4 GPUs and 1 EPYC Venice connected up to 12 scale-up switch ASICs across 6 trays, with graceful degradation if a link, a switch, or a whole switch tray dies.

They said the generation after this one goes optical, same timing as Rubin Ultra. AMD is not adopting 800VDC just yet, and the rack is a double-wide, whereas NVIDIA’s is a single-wide.

Intel Crescent Island

This is Intel’s new attempt at a datacenter GPU, and the design refuses every convention of the category: no HBM, air-cooled, PCIe scale-up. It carries up to 480GB of LPDDR5X on a 350W card (Intel’s own card ships with 160GB, partners can build up to 480GB), built on the Xe3P graphics IP with MX-format datatypes.

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The obvious question is who would use this. It looks useful for cost-sensitive, latency-insensitive work, but for that you want to batch aggressively, and to batch aggressively you want a big scale-up domain, which PCIe cannot give you. Maybe local and small-enterprise private workloads. The answer that makes the design cohere is prefill. Use it for prefill only, and you barely need memory bandwidth (prefill, the prompt-reading phase, is compute bound), while the 480GB of cheap DRAM holds enormous contexts, double the per-GPU HBM of the big rack parts. Pair it with an SRAM-based decode part and you have a disaggregated inference pair assembled from parts that dodge the shortages: no HBM allocation, no CoWoS, no liquid cooling, and no fight for TSMC capacity.

GPU Takeaways

The rack has long replaced the chip as the product, and the throughput-interactivity curve has long replaced per-chip specs as the scoreboard. Each vendor chose where on the curve to live: NVIDIA bundles the whole curve. AMD attacks the spec-per-megawatt middle, and Intel is off in the prefill corner that needs no exotic components. Component demand follows the same logic, since a rack is a fixed budget of megawatts and dollars being allocated among HBM, fabric, cooling, and power, and every vendor just showed you a different allocation.

The number from these talks I keep coming back to is Rubin’s 2x-versus-30x split, because it says the next year of platform improvement lands disproportionately on token speed rather than token cost. Faster tokens change product experiences, and better experiences drive usage, which is the demand feedback loop. Cheaper tokens change unit economics, which caps how much hardware each token can carry. Both are happening, but the vendors are engineering hardest for the first one.

Networking

Networking got 3 dedicated talks, and together they show the AI network is no longer one thing. The new vocabulary says it: scale-up inside the rack, scale-out between racks, scale-across between datacenters, and now scale-in between the GPUs and the services around them. Each layer is becoming its own product category with its own physics, and the fight in every layer is the same fight, proprietary co-design against merchant Ethernet.

Broadcom Thor Ultra

Broadcom’s NIC talk is the merchant side’s opening argument, and I got more out of it than I expected. Network interface cards (NICs) let GPUs talk directly to the scale-out network without going through a CPU, using remote direct memory access (RDMA) to read and write GPU HBM straight from the wire. This is also where the transceiver plugs in, which is why I track NIC count per GPU as an optics number.

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Thor Ultra is an 800G part on PCIe Gen6, 5nm, running 40-42W. The deck is structured as a confession list of what old Ethernet RDMA got wrong, each item now fixed per the Ultra Ethernet Consortium (UEC) playbook: no multipathing becomes packet spraying across up to 8 network planes, inefficient go-back-N retransmission becomes selective retransmission, and hard-to-tune congestion control becomes a programmable, receiver-credit-based scheme. Out-of-order packet placement is the clever bit, since sprayed packets arrive scrambled and the NIC writes them directly into their final GPU memory location instead of buffering to reorder. Their benchmarks on collectives (the all-GPU communication operations in training) land above 96% of line rate on 2 nodes, which is the number I would lead with if I were them.

NVIDIA BlueField-4

What does a DPU actually do? Data processing unit is not a very descriptive name; datacenter processing unit would be closer. It is a CPU that runs the infrastructure software (networking, storage, security) away from the main CPU so the main CPU can focus on the OS and applications. The deeper reason it exists is trust: the DPU is a server in front of the server, a separate processor with a separate OS, so the cloud operator’s control plane and the tenant’s code never share silicon.

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NVIDIA’s framing adds scale-in to the networking taxonomy: scale-up, scale-out, and scale-across connect GPUs to each other at varying distances, while scale-in connects GPUs to datacenter resources such as storage and security services. Agents made this a real traffic class, since an agent constantly hits databases, tool sandboxes, and context storage in between model calls.

BlueField-4 itself is a Grace CPU and a ConnectX-9 NIC on one package. The difference between an AI DPU and a traditional cloud DPU is the bandwidth: 7.2 Tb/s per compute tray, versus 200 Gb/s for the cloud DPUs of 2021. The talk also productized a 5-tier KV cache hierarchy (GPU HBM for active context, system memory for spillover, local NVMe for warm reuse, network storage for cold context), orchestrated by the DPU, with a claimed 5x power efficiency on context storage.

NVIDIA Spectrum-X

Spectrum-X is NVIDIA’s Ethernet scale-out, custom designed for higher bandwidth and lower jitter (variance in latency), and per the talk by now well ahead of Infiniband in adoption. Multi-tenancy is when one fabric carries multiple jobs at once, and Spectrum-X was designed for it specifically, with 1.9x better training performance in a multi-job environment against off-the-shelf Ethernet. The single-job gap is only 1.2x, and that spread is the whole product: the value shows up when neighbors get noisy, which in a real cloud is always.

NVIDIA’s optics section answered a question I have been asked a lot. We know why you need CPO (co-packaged optics, moving the optical engines from pluggable modules onto the switch package itself) for scale-up, but why for scale-out, which is already optical? The answer is power. Co-packaging eliminates the DSP (the signal-processing chip that exists to clean up the signal after the long copper trace from switch ASIC to faceplate). NVIDIA’s photonics numbers are 5x lower power, 4x fewer lasers, and 10x better reliability, on TSMC’s COUPE process, in production. They also sized optics at about 10% of an AI factory’s compute power, which is the sharpest TAM framing I have seen anyone hand the optical industry.

The main event is the multiplane topology. Traditional scale-out gives each GPU 1 fat port: a 102.4 Tb/s switch configured as 64 ports of 1.6T serves 64 GPUs per switch. The trick is configuring the same switch as 512 ports of 200G instead, and giving each GPU 8 thin ports into 8 independent network planes. Each GPU keeps the same total bandwidth, and the fabric now reaches 512K GPUs, 64x more, since 2-tier network scale goes with the square of switch radix (the port count). Any single link failure now costs a GPU 1/8th of its bandwidth instead of all of it.

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So this does a few things. First, the network becomes WAY more reliable, with 90% bandwidth retained through failures that take off-the-shelf Ethernet to 0, and 400x faster failure detection. Second, you need 1.7x fewer switches, which is bad for optics counts per GPU even as it enables the giga-scale clusters that grow optics in absolute terms.

Networking Takeaways

The fabric is following the same script as the compute: disaggregate the general thing into specialized layers, then fight over each layer separately. NVIDIA is ahead on co-designed behavior under load, with the merchant camp standardizing each generation’s tricks about 18 months behind.

The component read is that networking intensity per GPU keeps rising across every layer (a NIC per GPU becoming several, a DPU per tray, 8 planes per GPU), while 2 of these innovations (multiplane switch reduction, CPO laser reduction) cut content per port even as cluster scale explodes port count. Optics remains a volume story with a mix headwind, and the switch and NIC silicon remains a straight beneficiary regardless of which side wins the protocol argument.

ASICs

The last theme is the insurgents: 2 startups, a hyperscaler with a decade of silicon behind it, and a frontier lab that had never built a chip. All 4 talks share a diagnosis: decode is memory bandwidth bound, and general-purpose GPUs waste most of their bandwidth on it. All 4 share a prescription: SRAM close to compute, plus a topology tuned for low latency. The disagreements are about how far to push it.

Cerebras CS-4

Cerebras announced CS-4, and the announcement drew little attention. I think that is a mistake.

CS-4 moves from 1 wafer to 3 WSE-3 Turbo wafers per system: 750 PFLOPS (6x the CS-3), 132GB of on-wafer SRAM, and 129.6 PB/s of memory bandwidth, with new direct wafer-to-wafer links at 2 microseconds of latency.

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The architecture is the purest possible bet on the bandwidth thesis: keep the entire model in SRAM spread across the wafer, and the bandwidth number becomes 6,000x a Rubin GPU’s HBM. The cost is capacity, 132GB against 21TB in an NVL72 rack, so big models pipeline across wafers with only activations (the small intermediate results flowing between model layers) crossing between them, at less than 0.2ms per hop on a 10T-parameter model. That trade is why Cerebras owns the far right of the throughput-interactivity curve.

They also announced CS-6, which puts hybrid-bonded DRAM on the SRAM wafer. Enormous memory bandwidth with almost no memory capacity is the entire Cerebras limitation, and CS-6 is an attempt to remove it. If they solve the thermal issues associated with bonding DRAM to the wafer, the addressable market changes completely.

SambaNova SN50

SambaNova’s argument is that decode is the bottleneck for inference, and HBM bandwidth is the bottleneck for decode. Most of the HBM bandwidth on a GPU is spent moving data that is neither weights nor KV cache. They built a metric around it, model bandwidth utilization (MBU), the fraction of peak memory bandwidth doing useful work, and their measurements put GPUs at 5-25% while the SN50 holds 44-51%.

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So they built SN50 as a decode specialist: 432MB of on-chip SRAM, 64GB of HBM per chip, and the software and chip design tricks that raise MBU. The 2 big ones: compiling the entire model into 1 persistent kernel (no kernel launches, no synchronization gaps, intermediates never round-trip through HBM) and spatial dataflow (lay the operator graph out physically across the chip and stream data through it, rather than time-slicing 1 big engine). The scaling claim is that MBU stays flat as chip count grows, 200 to 500 tokens per second per user from 64 to 256 chips, where GPU utilization collapses with scale.

Google TPU v8

Google’s change for TPU v8 is making 1 chip for training and 1 chip for inference, TPU 8t and TPU 8i, after a decade of alternating between the 2 on a single line.

The inference chip carries more HBM bandwidth per unit of compute, because decode is bandwidth bound. The 8i also carries a lot of SRAM (384MB, 2.4x the prior generation), plus 288GB of HBM3E in 12-high stacks. Their SRAM-versus-HBM table gives the whole custom-silicon story its numbers: 15-20x the bandwidth, 100x lower latency, 10-20x better energy per bit.

The networking topology is the other change. The 8i uses a new arrangement they call BoardFly, 1,152 chips per pod with a maximum of 7 hops between any 2, versus 16 hops in the old 3D torus. The point of fewer hops is lower latency, because MoE all-to-all traffic is bound by network latency. They also put collective operations into the interconnect die itself, cutting another 5x of latency.

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In training you need bisection bandwidth instead (the bandwidth across the middle of the network when you cut it in half), so the 3D torus remains, with lots of optical circuit switching (OCS). Training needs lots of FLOPS and lots of shared memory: the 8t superpod is 9,600 chips sharing 2PB of HBM at 121 exaflops, any slice size carved on demand through the OCS layer, as typical of Google.

OpenAI Jalapeño

OpenAI closed the conference with Jalapeño, the inference chip it had announced the morning of day 2.

They taped out in 9 months with an extremely small team, and one of the first things they said was that their internal AI system helped them build the chip. There was barely any traditional chip design experience on the team. The chip itself: a compute die with an I/O chiplet and 6 HBM4 stacks, 216GB at 15.4 TB/s per chip, 700W, designed for OpenAI’s inference workloads. It was designed around speculative decode, which is using a cheap draft model to predict several tokens ahead and then checking them with the main model in 1 batched pass, turning 8 serial trunk passes into 1.

They built it for both prefill and decode and for both throughput and interactivity, trying to be the Pareto frontier everywhere, and the benchmarks are aggressive in the right way: power-normalized comparisons on the public SemiAnalysis InferenceX suite, on models never co-designed for the chip, with Jalapeño running plain single-token prediction against GPU baselines allowed speculative decoding. They claim the frontier anyway, 1.7x tokens per kW over GB300 on DeepSeek R1 with 3.6x lower latency, which is a remarkable result for first silicon. The improvement is much bigger on the high-interactivity side than high-throughput, same shape as everyone else this year.

A rack holds 128 Jalapeños, over 1 PB/s of aggregate memory bandwidth, in the same neighborhood as a VR200 NVL72, with Broadcom Tomahawk 6 for the network. The smartest thing they did, though, is the process rather than the chip.

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They kept the team tiny so it could move fast. More importantly, they built a new hardware description language, similar in spirit to Rust, designed so AI could write correct code out of the box, and ran an internal AI optimization system over the design from functionally-correct to beyond-expert performance. They went from RTL freeze to tapeout in 9 months and from first silicon to serving ChatGPT in 10 weeks, with generation 2 already approaching tapeout.

ASIC / Inference Startup Takeaways

The insurgents used to be a zoo of incompatible bets, and this year they converged: big SRAM, low-hop topologies, decode specialization, and a seat on the throughput-interactivity curve chosen in advance. Convergence means the architecture argument is settling and the fight is moving to manufacturing access, software maturity, and capital. That fight favors the players attached to hyperscaler balance sheets (TPU, Jalapeño, and the acquired Groq) over the independents selling into the same sockets.

Conference Takeaways

My top 4 conclusions for Hot Chips 2026.

Capitalism Is Coming for the Memory Markup

There is a staggering amount of innovation happening in the memory layer right now, and the reason is price. Memory makers are extracting something like 90% gross margins on HBM-class products, which is a 10x markup over cost, and this is classic economics: when a markup like that exists, the forces of capitalism combine to destroy it and relieve the shortage. That is easy to say in a business school macro way, and it is a different thing entirely to shrink down to the micro level and watch 1 building block of the process actually happen. This conference is that building block: Samsung putting logic in the base die, d-Matrix stacking compute on DRAM, SanDisk-aligned HBF stacking NAND like HBM, Samsung again with logic inside LPDDR banks, XCENA with compute on the CXL expander, Cerebras bonding DRAM onto wafers, and every accelerator vendor substituting SRAM for HBM wherever the workload allows. All the HBM despec talk you hear in the market is the same force wearing supply-chain clothes: buyers redesigning systems to need less of the expensive thing per token.

None of this lands in time to break the current cycle, since all of it is 2-4 years from volume, and several of the escapes (HBF, HBM4 base dies) actually consume more wafers per bit on the way. So the near-term shortage stands. The medium-term lesson is that the markup is rented, and the rent is being contested from 6 directions at once. The memory makers know it, which is why Samsung’s entire conference presence was about climbing the value stack before the commodity layer gets arbitraged.

Disaggregation Is Eating Inference

The second theme I could not stop seeing: inference is being taken apart into phases, and each phase is getting its own hardware. At the high level, prefill and decode split, since prefill is compute bound and decode is memory bandwidth bound, and running both on the same GPU wastes one resource or the other. Intel built Crescent Island explicitly for the prefill side. SambaNova, Groq, Cerebras, and d-Matrix built explicitly for the decode side. NVIDIA productized the split inside its own platform, with the LPX drafting tokens and Rubin verifying them, and BlueField tiering the KV cache underneath. One level lower, the same knife cuts again: attention offloads to near-memory devices (the XCENA demo), experts spread across cheap-capacity memory (the HBF case), and speculative decode splits the token loop itself (Jalapeño’s whole design center).

You see the throughput-interactivity curve in basically every deck, and that repetition is the tell. An immature industry built maximally general chips because nobody knew how the workload would evolve, and now that the workload is legible, everyone is pulling the general thing apart and squeezing each piece. The engineering trades are additive: the same hardware resources serve meaningfully more tokens after disaggregation, since each phase runs on silicon shaped for it.

If you assume chips and memory scale proportionally with token demand, disaggregation breaks it, since the industry is actively figuring out how to serve more tokens per unit of everything. Efficiency gains this large usually resolve through Jevons dynamics, cheaper and faster tokens creating more than proportional token demand, and that has been the right bet at every prior efficiency step. But the composition of demand shifts even when the total grows: decode-specialized silicon carries different memory (more SRAM, sometimes no HBM), prefill tiers carry cheap LPDDR instead of HBM, and KV cache migrates down the storage hierarchy toward NAND.

AI Is Coming for Chip Design Itself

OpenAI’s talk was, I think, the most important 30 minutes of the conference, mostly for reasons that have nothing to do with the Jalapeño chip. The talk showed a tiny team with barely any silicon veterans, a custom AI-friendly hardware language, an internal AI optimization loop, and RTL to tapeout in 9 months, landing a part they credibly claim beats the incumbent on power-normalized inference. Chip design has been defended by scarce talent compounding inside a few companies for 40 years. It also happens to be a nearly ideal domain for AI: fully digital, simulation rich, and verifiable at every step, so an AI can check its own work the way it cannot in most of engineering.

Over the long term I think this is pretty bearish for any fabless chip designer whose moat is design talent and iteration speed rather than ecosystem lock-in. This feels like how chip design should be done. In software, a giant corporation with 2,000 engineers is exactly who gets disrupted when a small, AI-native team with a proper harness can ship the same artifact in a fraction of the time, and semiconductor design might not be too different. The giants have the talent today, but talent can be poached, and harnesses can be copied. The moats that survive this are the ones AI does not compress: manufacturing access and allocation, installed software ecosystems, customer relationships, and fabs. That is roughly NVIDIA’s actual moat stack (CUDA, NVLink, supply relationships). A mid-tier ASIC vendor has almost none of it, and its entire value proposition (design execution as a service) is the thing that just got cheaper. EDA is the second-order question: the volume of design starts goes up, while value per seat gets contested by exactly the tools the labs are building for themselves.

Leading Edge Is for Logic Only

The fourth conclusion is one I had to assemble from 4 unrelated talks: the leading-edge wafer is becoming a scarce input reserved for the transistors that actually benefit, with everything else partitioned onto trailing nodes and rejoined through advanced packaging. Fujitsu put under 30% of MONAKA’s silicon on N2, with the SRAM and I/O on 5nm, because SRAM and analog stopped shrinking. AMD did the same to the MI455X, N2 for the compute dies and N3P for everything else. Samsung’s whole custom HBM pitch is moving the base die to whatever node earns its keep, and Intel built Wildcat Lake’s cost story on organic packaging and right-sized dies. Nobody presented this as a shared thesis, and it is one.

Thus, this could mean leading-edge wafer demand per chip grows much slower than transistor counts suggest, while packaging intensity (hybrid bonding, die-to-die interfaces, substrates) grows much faster. That is structurally bullish for the packaging and bonding toolchain and for trailing-node capacity utilization.

thanks for reading. if enjoyed, like repost and follow!

There was some spicy news this morning about a spicy chip from a spicy frontier lab who will be the last presenter today at Hot Chips.

Mamma mia

follow me on on X: x.com/jasonschips

Contents

1. Samsung LPDDR5X Processing in Memory

2. XCENA MX1 CXL Computational Memory Device

3. Thor Ultra: Ethernet NIC Chip

4. NVIDIA BlueField-4 DPU

5. NVIDIA Spectrum-X Multiplane Network Architecture

6. Cerebras CS-4

7. SambaNova RDU

8. Google TPU v8

9. OpenAI Jalapeno

Samsung LPDDR5X Processing in Memory

We have memory themed presentations again today.

Samsung will not stop shilling processing in memory (PIM). Honestly very reasonable. They are really the only ones who can do this and benefit from it.

PIM just means a small logic block next to each DRAM memory bank.

It can support 8x the bandwidth of LPDDR5X. If you add processing you can just send only the data that needs to go back to the main processor.

Can apparently be used for both server and edge.

Yeah this is pretty darn cool. Dunno what the actual cost of something like this is from Samsung but you def see the potential.

XCENA MX1 CXL Computational Memory Device

Jointly presented by Samsung as well. CXL is memory pooling that improves utilization of memory and expands memory arbitrarily. SSDs are seen by software as actual memory and DRAM serves as cache. They call it infinite memory for a reason. Generally very bullish for NAND since it invites it to DRAM’s memory tier by solving some of the latency problem.

MX1 is a “memory accelerator” near memory compute chip that enables this stuff. So again, you have Samsung shilling compute with memory. Not PIM but near memory compute and happens to be fabbed by Samsung lol.

Funny enough they use RISC-V. This is a CPU with many small cores that has nowhere near the TFLOPS of a GPU but is also kinda programmed like a GPU?

Again, when you have processing near memory you get much higher effective bandwidth.

Claudeslop ELI5:

Your files are in the basement.

Local DRAM — filing cabinet beside your desk. Fine, but you can only fit so much there.

Over CXL — you needed more room, so the files moved to the basement. Now every question means carrying boxes up the stairs. Slow, and exhausting.

MX1 — hire someone who lives in the basement, reads the files there, and sends you only the answer.

Broadcom Thor Ultra: Ethernet NIC Chip

Broadcom’s NIC. Network Interface Cards (NICs) allow GPUs to talk directly to the scale-out network without going through a CPU. They use Remote Direct Memory Access (RDMA) to directly access GPU HBM. This is also where the transceiver plugs in.

This is the chip.

NVIDIA BlueField-4 DPU

What does a DPU even do? A data processing unit is not a very good name. Think a better name is datacenter processing unit. It is just a CPU that runs the infrastructure software workloads away from the main CPU so it can focus on OS and apps. “Networking, storage, and security.”

Scale-up, scale-out, and scale-across connects GPUs to each other at varying scales. Scale-in (which uses DPUs) connects GPUs to datacenter resources such as storage and security.

Bluefield 4 is made up of a Grace CPU and a ConnectX-9 NIC. Basically the difference between an AI DPU and traditional cloud DPU is the insane bandwidth. Bluefield 4 has 7.2Tbps.

NVIDIA Spectrum-X Multiplane Network Architecture

Now this is the fun one.

Spectrum-X is Nvidia’s ethernet scale-out. Custom designed for higher bandwidth and lower jitter (variance in latency). Way more popular than Infiniband.

Multi-tenancy is when one fabric handles multiple jobs. Spectrum-X was specifically designed for this and has 1.9x better performance in multi-tenancy.

We know why you need CPO for scale-up. But why do you need it for scale-out? It’s already optical.

The answer is power.

CPO low power because you eliminate DSP to correct the degraded signal from the long copper trace to the faceplate because it is co-packaged.

Now onto the main even which is multiplane networking architecture.

Traditional scale-out is one port per GPU. Say you have 64 1.6T ports on your switch for 102.4 Tpbs total bandwidth (which is what Spectrum-X switch actually has). You can do a neat trick where you have 512 200G ports instead and each GPU gets 8 ports or more specifically access to 8 planes of network, each with one port of 200G.

So what this does is a few things. First, the network becomes WAY more reliable. Second, you need less switches which is bad for optics. 1.7x less to be precise.

Cerebras CS-4

Cerebras doin an announcement

No one cared.

Looooook at our chip! It’s so big

Big chip big improvement.

Now with rack that has 3 chip.

Ok no more slop.

They also announced CS-6, which has hybrid-bonded DRAM on the SRAM wafer. If they can solve the thermal issues associated with this and actually get it to work, they’ll be a huge company. Think about it: insane memory bandwidth, but zero memory capacity. If you solve the capacity problem, the world is in your hands.

SambaNova SN50 RDU

SambaNova basically says decode is the bottleneck for inference and HBM bandwidth is the bottleneck for decode and most of the HBM bandwidth is spent moving stuff that ain’t weights or KV cache.

So they built SN50 to be a decode beast. Lots of SRAM and some software/chip design tricks (one kernel for whole model, spatial dataflow).

Google TPU v8

Google’s thing for TPUv8 is making one chip for training and one chip for inference.

TPU 8t and TPU 8i. Can you tell which is which?

Hint: Inference need more HBM bandwidth per unit of compute because decodeeeee.

Also lots of SRAM because memory bandwidth.

Look at their networking topology. This is to minimize hops to minimize latency.

In training you need lots of bisection bandwidth so 3D torus still used. Lots of OCS.

Training needs lots of FLOPS and lots of shared memory.

9,600 all-reduce scale-up domain 2PB total memory as typical of Google.

OpenAI Jalapeno

Last and VERY CERTAINLY not least.

SemiAnalysis

OpenAI Jalapeño: Better Than Nvidia Blackwell

OpenAI has spent the past couple years quietly building “Jalapeño,” an inference chip just announced at Hot Chips. Rumors of a successful tapeout had been swirling for a while. But now we have details. OpenAI invited us to look at their chip, go to their labs to check out how real it is, and…

Read more

a month ago · 130 likes · Bryan Shan, Myron Xie, Jordan Nanos, Wega Chu, Clara Ee, and Dylan Patel

They taped out in 9 months. Apparently an extremely small team too. And one of the first things they said was ASTRA helped them build this thing. No chip design experience! Let’s think about what this means for the moats in the space.

It was designed for speculative decode which is using a cheap draft model to predict several tokens ahead and then check with the main model.

They built this thing for both prefill and decode and for both throughput and interactivity. Trying to be the pareto frontier everywhere.

THIS IS REALLY IMPRESSIVE.

Much bigger improvement on high interactivity side rather than high throughput.

They have 128 jalapenos in a rack with over 1PB of total memory bandwidth (similar to VR200 NVL72).

But the smartest thing they did has nothing to do with the chip itself. It’s their process.

They took a tiny team and had them move fast which I think everyone agrees is better than bloat. But most importantly, they made a new hardware language (!!!) which is kinda similar to Rust so AIs could write correct code out of the box.

But over the long term I think this is pretty bearish any fabless chip designer. This feels like how chip design SHOULD be done. Like with software you are bound to be disrupted if you’re a giant corpo with 2000 engineers and some 19-year-olds can vibe code your shi, as that is how SWE should be conducted. Small, pilled, AI-native team with chip design harness and custom language can easily disrupt the industry. And maybe the giants have the talent today but talent can always be poached…

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Hot Chips is indeed hot.

Fun fact: Stanford dorms have no AC. Stanford offers student housing to Hot Chips attendees, so I am staying in the dorms for the duration of the conference. However, what I didn’t know is that for whatever reason this academic institution with a $50b endowment has no air conditioning. So I have been getting really hot during Hot Chips. It’s kind of hard to write when you’re overheating.

Today’s session is all about processing units (PUs). Both the central (C) and graphics (G) kind. This somehow turned out very LONG.

Contents

1. IBM Z & LinuxONE Processor CPU

2. Intel Core Series 3 Wildcat Lake CPU

3. Nvidia Vera CPU

4. FUJITSU-MONAKA Arm-based CPU

5. ARM AGI CPU

6. Intel Diamond Rapids CPU

7. NVIDIA Rubin GPU

8. AMD Instinct MI400

9. Intel Crescent Island GPU

IBM Z & LinuxONE Processor CPU

I was late and joined in the middle of this and had no idea what was going on but I will still cover this.

IBM is getting into the CPU game! They are making ARM CPU. Well it is actually dual ISA and executes both z/Architecture and Arm v9.3 natively, in hardware, on the same core. Apparently very high single-core performance for an ARM CPU. Very next-gen so not happening anytime soon. Sort of like ARM AGI?

Intel Core Series 3 Wildcat Lake CPU

This is a chip for computers. Not the ones that are racked up inside datacenters, the ones that actually go on your desk. This is a chip that was already released earlier this year.

It is an ultra-series architecture for their entry tier chip. Fabbed on 18A. Packaged using Foveros in this chiplet on silicon interposer-like architecture. I personally am not that interested in non-AI-DC stuff.

Nvidia Vera CPU

The first really interesting and directly AI stonk relevant presentation.

Nvidia presentation slides are so Nvidia. Many Nvidia-isms.

The core pitch for Vera CPU is maximal single-thread performance. This is the bet that agentic workloads need minimal latency and don’t care too much about throughput like desktop multitasking.

Speeding up common agent shenanigans like headless browser use.

Therefore the tradeoff is simply to make a BIG CORE.

They have a type of multi-threading (multiple instructions on one core) that is not SMT (“traditional” simultaneous multi-threading) called spatial multi-threading (coincidentally also SMT). Spatial just means the threads sort of use different resources and are segregated so it’s deterministic and gives you better single-thread performance. That’s what you get with big core.

They also designed for power efficiency with lower power cores and LPDDR5X.

The thing is built out of 6 dies. The big central die is the massive Olympus cores.

But alas, there are always tradeoffs. There is no free lunch. You have to look at what specs they presented and what they left out, and compare it to AMD EPYC and AWS Graviton.

SMT is statistically more efficient so you’re trading absolute performance/reliability with overall efficiency. It also requires more area. So Vera has like 1/2 the total cores of an EPYC or Graviton.

LPDDR5X is lower power but it is also soldered which means capacity ceilings vs socketed DIMM and worse serviceability.

FUJITSU-MONAKA Arm-based CPU

This is a Japanese company tryna do CPU.

Their core pitch is not using N2 for everything and instead splitting it as N2 for core die and 5nm for SRAM and IO and connecting the chiplets via hybrid bonding.

Apparently this optimizes for cost and power consumption.

But also, core dies on the opposite sides of the chip?? This raises an interesting question about core-to-core latency.

Anyways the TLDR is cheap Japanese chip.

ARM AGI CPU

ARM makin’ a chip for the first time instead of just licensing stuff. Before you can use their Neoverse cores for your own stuff (but people don’t like Neoverse for some reason). So they’re using their own IP to make their own chip. This is not new it was announced in the spring and people talked about it a lot then forgot about it.

Depending on whether or not you like ARM, you can call this chip balanced (or boring), pragmatic (or unremarkable), and well-rounded (or mid). They are not taking a view on the market like Intel or Nvidia. The more important takeaway is that they are making a chip in the first place.

Intel Diamond Rapids CPU

They are using this fan-out fabric architecture. Basically a bunch of compute “building blocks” surrounding a central I/O and memory “fabric hub”.

It is very scalable because you can add more compute building blocks to one chip.

As a result you get an unhinged amount of cache (1.28GB), cores (256), and threads (512).

This is 3x the cores of Vera (88) and more than EPYC/Graviton (192). For cache it is 5 MB of LLC per core vs Arm AGI at 2.9MB, Vera 1.9MB, Graviton5 0.94MB.

This chip is the polar opposite of Vera. Intel is most definitely taking a view on the market. But it’s not like they say it is for another workload. It is for agentic too! They just shill different specs.

And then every part of the chip is Intel-made including the packaging. No TSMC.

NVIDIA Rubin GPU

Hmmm the performance boost of Rubin over Blackwell is actually bigger on the high-interactivity (fast speeeeeed) side than the high-throughput one. 2x throughput in low interactivity while 30x throughput in high interactivity. We’ll see much faster tokens in a year.

Likely because Groq LPX disaggs the decode and speeds it up. When you wanna go fast and you are bottlenecked by memory bandwidth you turn to super speedy SRAM.

“No one uses a single chip”

It’s about the AI factory is a classic Nvidia-ism. High key I agree.

Rubin comes with adaptive sparsity. The relevant background is that quantization (whether your model weights are FP16 or 16-bit floating point numbers or like FP8 like how many significant digits your numbers have) is actually specific to the hardware and needs to be supported by the hardware. So they went from FP16 → FP8 → FP4 with Blackwell, but you can’t go to FP2 because you just can’t because you lobotomize the poor model.

So they invented adaptive sparsity. It’s basically taking the model and dropping the stuff that is near zero to make it half as big and replacing it with metadata.

NVFP4 here is actually a less quantized version of FP4. So it’s in between FP8 and FP4 and uses adaptive sparsity.

This is actually important because part of the software platform is specific to the hardware generation.

They also do sparse attention where you only do attention on tokens that matter instead of on every single token. Natively supported on Rubin. Basically taking a bunch of inference optimization software tricks and baking them into the hardware.

NVLink is a pretty important moat for Nvidia.

Large scale-up domains allow your racks to mog in the high throughput (cheap token) side of the curve. Via expert parallelism. Bigger scale-up domain means bigger batches. It’s the opposite of the Groq LPX.

Some features of the rack: No optics (yet), 800VDC (sidecar), minimized cables, waste-less-stuff cooling, and smooth out your power with capacitors.

AMD Instinct MI400

AMD made a discount NVL72 that’s maybe not so discount.

AMD’s rack actually beats or ties Nvidia VR200 NVL72 on pretty much all the specs. FP4 FLOPS and scale-up bandwidth are tied but AMD wins everything else.

Especially memory capacity and scale-out bandwidth. The racks are almost the same power so technically you get denser per-MW performance. This is the AMD leapmog getting around whisper world.

What Nvidia has that AMD still doesn’t is NVLink. A good protocol co-designed with all your GPUs (and not open standard) is very important because when you do all-to-all the speed of the system is the speed of the slowest participant so you need to cut the tail.

And CUDA… but Nvidia doesn’t talk about that very much anymore. Wink wink.

Notice the key differences between the Nvidia and AMD presentations. Nvidia focused purely on system level performance type stuff while AMD’s slides are a giant spec sheet. It makes sense when you think about it. Nvidia, as the incumbent, has all of the models and software codesigned around it and thus can leverage its maturity to performancemaxx. The only way AMD could catch up is mogging in pure specs.

Next they did their system-level presentation. This is their scale-up pod architecture. Each one of these is one tray. 4 GPUs one EPYC connected to the scale-up switch.

They said the next gen after this one will have optical. So same as Rubin Ultra.

Not adopting 800VDC just yet. Also rack is kinda fat whereas Nvidia’s rack is skinny.

Intel Crescent Island GPU

This is Intel’s new attempt at datacenter GPU.

So it’s a no HBM, air-cooled, PCIe scale-up datacenter GPU! I am tryna think of who would use this but am coming up empty handed.

Intuitively it seems useful for not-latency-sensitive but very cost sensitive stuff. But for that you’d just want to go batch like crazy. And to do that you want big scale-up domain that you can’t get with PCIe scale-up.

Maybe for local/small enterprise private workloads?

Oh you know what I got it. If you just use this thing for prefill, you don’t need memory bandwidth. And then they have SambaNova’s SRAM widget for decode. Gonna be high interactivity expensive tokens only but could work? It also has 480GB of DRAM which is like double per-GPU HBM. Also it doesn’t need TSMC allocation because yk.

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Hot Chips is a based 3-day conference with a bunch of presenters and each day has its own distinct theme. Day 1 (today) is memory.

Very first thing you’ll hear about is how bad the memory shortage is lmao. It’s like 70% of a rack at this point and clearly the elephant in the room.

Not exactly the most bullish thing for DRAM makers if everyone at giant industry conference is dedicating their career to reducing price of your product.

For me and my conference coverage the idea is that I am not gonna immediately take a side and opine on whether or not something will work or will not work. I am investor not PhD. But what I will do is try to make these things as easy as humanly possible to understand via unfiltered brain dump.

Also, a funny theme to notice is that every company that presents just shills their own stuff. Like Samsung is gonna shill HBM-based die and processing in memory because guess who is the only memory maker with their own leading-edge foundry supply? SK hynix shills HBM because, well, they are SK hynix.

Contents

1. HBM Basics

2. Processing In Memory (Samsung)

3. HBM Packaging (SK hynix)

4. 3D DRAM (d-Matrix)

5. High Bandwidth Flash (OXMIQ, PRAXMATI)

HBM Basics

Most of you know this but I always think it’s worth going over the fundamentals. High bandwidth memory has high bandwidth because it’s very parallel.

Therefore die needs to be bigger in order to allow this parallelism which contributes (but is not all of) to why HBM eats 3x die area vs DDR.

This conference (Hot Chips) was named after the main problem with HBM. which is that the chips get really hot.

The problem is pretty intuitive actually. The cooling is on top not the bottom but the base die processor which creates the heat is all the way at the bottom therefore chip gets very hot. Reliability degrades at high heat.

Some HBM stats:

Processing In Memory

This is fascinating. General idea is that if you can do some computation on the base die, you have to send less data from HBM to logic die. Think about if you’re doing a complex math problem, instead of sending the entire starting problem back and forth between the memory and the processor, if the memory can get you to an intermediate solution already, you would only need to send that intermediate solution over to the processor. There is much less I/O.

It is necessary because compute is scaling faster than HBM memory bandwidth. And decode (attention/FFN) is memory bandwidth bound so this is the exact thing you don’t want.

By reducing data transferred you also help the power requirement and therefore the thermals.

HBM base die currently is only a passive router, so arguably we can make it work harder. It only handles the communication channel to the compute die (the PHY) and test functions for the DRAM stack.

In the future base die can do a lot more stuff like the memory controller (moved off the xPU, freeing that area for compute), RAS sensors and self-test, connecting external memory directly through the base die, and eventually processing elements that do compute in the base die itself.

This also makes HBM a much more customized and less commoditized product.

This is obviously great for Samsung who has their own advanced logic foundry and doesn’t have to beg TSMC for allocation (like hynix and Micron) and also happens to make HBM. Also leading edge logic base die reduces power.

They can do this by reducing HBM PHY (portion of chip dedicated to the physical I/O interface that talks to the GPU) region. On advanced logic, the PHY shrinks to a small D2D interface. That frees up the rest of the die.

The challenge again is thermal hotspots due to higher power density.

And they actually have a pretty smart solution for this. PHY is hot. PHY is also on the side. So why not extract heat from side instead of top?

Next is zHBM. This is a common 2030+ type hype technology. Requires hybrid bonding and rocket science.

For ultimate bandwidth hack, just stack HBM on top of the XPU.

Can also reduce power significantly. Which is necessary to save thermals. Would also be 4 hi instead of 8 hi also in order to save thermals. So thermal issue might actually not be as big of issue.

Packaging

I still remember the days when MR-MUF was part of hynix moat thesis. SK hynix actually uses TC-NCF in HBM4 now.

I don’t think there was anything too new about this presentation. This is the stuff that they’ve been doing since 2023 and doing a good job at.

3D DRAM

This presentation was objectively great. Very easy to follow and understand. Here goes my explanation.

SRAM is very fast but too big and expensive.

High Bandwidth Memory isn’t high bandwidth enough (but has great capacity).

d-Matrix solution is stacking compute on memory which they call 3D DRAM. High bandwidth because no beachfront limitation and high capacity because it’s still DRAM.

Most of inference time is spent on decode which is memory bandwidth bound.

Pitch is 3D DRAM = speedy inference that doesn’t bankrupt you.

This is actually really compelling. It’s not even funny. It’s like everyone’s breaking their neck trying these esoteric solutions, and these guys are literally saying to just stack logic on DRAM. It’s too simple: no multiple layers (it’s just one layer), no hybrid bonding. Just. Stack. The. Damn. Logic. On. DRAM.

High Bandwidth Flash

HBF is 8-16x the capacity of HBM.

But $/GB isn’t true TCO. What people actually care about is $/token. So you have to consider the tradeoff of bandwidth/latency which is 25x worse.

Memory bandwidth is important when you have high batch size (high throughput) and high interactivity (speedy inference). They are the opposite sides of the same tradeoff, so it is when you are pushing the Pareto frontier.

This graph is awful but maybe someone will find it helpful.

When you are trying to push that Pareto frontier you are memory bandwidth constrained and HBF will have tons of unused capacity.

HBF only useful for low batch size thus low bandwidth demand scenarios when you can use fewer GPUs & HBF stacks to serve the same tokens. So you can fill up the entire HBF.

Think about a small personal local or private enterprise workload. Smol box not big rack.

Another interesting use case is expert parallelism where in the FFN stage you put multiple experts on separate GPUs.

HBF thrives here because you cut down the amount of communication that is needed because more of the experts that are in the same place.

For HBF I was bullish going in but now am slightly less bullish and have more realism. If you haven’t seen Sandisk Investor Day they PUMPED. But it’s SanDisk. No, HBF does not have the same bandwidth as HBM. There is, in fact, a trade-off. But think about how mature the HBM ecosystem is and how much R&D has been poured into that, versus HBF. The fact that there are a few niche use cases today is kind of bullish because that means, as the software matures, as the systems get figured out, and as the actual design of the chip gets perfected, the HBM to HBF trade-off will start to go in HBF’s favor.

But if anything interesting does come up there NAND won’t even moon it will Mars. Think about it. HBM is like a 9x trade ratio because first you need SLC and not TLC and second you need to stack them like HBM.

Sorry for being quiet. Compliance is hard. But now that it’s figured out, posts start again TODAY. Conference coverage (Hot Chips and Semicon).

Everyone also gets a refund (prorated for any subscription time remaining after August 1 when Jason’s Chips became free, to request a refund, please email jasonschips@gmail.com from your Substack email).

Best regards,

Jason

Robotics = AI.

Just 4 years earlier in development and physical rather than digital.

Every concept in robotics has a parallel in AI, and these parallels are accurate, structural, and one-to-one to the point where it’s truly uncanny. Both are general purpose automation technologies, and in the universe, these are the only two in existence because there are only two types of activities to automate: digital and physical. This entire article will be mapping every concept in robotics to its AI counterpart, and you will see how much easier it makes intuitively understanding this technology and its future market potential.

Introduction

Why should two such different technologies rhyme this precisely? Because they both fully generalize to a human capability set, and in doing so replaces human labor rather than merely augmenting it.

In 1965 the mathematician I.J. Good wrote that “the first ultraintelligent machine is the last invention that man need ever make,” because a machine that can design machines will design its successors and leave human intelligence behind. Almost everyone who quotes this assumes there is one last invention, and that it is AI.

There are, in fact, two last inventions, because thinking and doing are separable, and AI only does the thinking. It doesn’t matter how many geniuses you can cram into a data center. They literally cannot move a paperclip. You could say, “Oh, they must be smart enough to design a humanoid robot to do it for them so humanoids are just a byproduct of AGI.”

However, let me ask you this: How would an AGI manufacture that humanoid robot? Does it have supply chain relationships? Can it build factories? Can it pour concrete? Yeah, that’s what I thought.

The second last invention is the general-purpose humanoid robot. Artificial General Robotics. Instead of an AGI, it is AGR. Together, and only together, the two cover the whole of human labor.

Most general-purpose technologies (electricity, the smartphone) augment. These two replace, and replacement is what creates a singularity. Technologies of that kind (of which there are only two) obey the same patterns: the same stages of autonomy, S- or L-curve, economic singularity, RSI, Moravec’s Paradox, and even very suspiciously similar big three labs.

The Second Singularity is coming — the physical singularity.

Welcome to A General Theory on Humanoid Robotics.

Contents

1. The Four Stages of Robotics

2. The Four Stages of AI

3. The Big Three Labs

4. The Elbow of The L-Curve

5. Moravec’s Paradox

6. VLAs vs. World Models

7. The Economic Singularity

8. Robotic Self-Improvement (RSI)

9. Conclusion: Predicting ChatGPT and Claude Code Moments

Beep beep boop boop beep boop beep boop terms and conditions. Beep boop not financial advice.

The Four Stages of Robotics

Robotics comes in four stages, each one more general than the last.

1. Caged Arms

2. Cobots (Collaborative Robots)

3. Autonomous Mobile Robots

4. Humanoid Robots

Each stage is its own market. And the difference between the markets is as follows: The more general the robot, the less of the world you have to redesign to use it, and the more exponentially it spreads.

Why do more autonomous and general robots grow exponentially? It is simple. Either the environment is rebuilt around the robot, or the robot adapts to the environment. The environment is expensive and glacial to change. Thus, the robot, as it generalizes, gets cheap and fast to deploy into environments it’s never seen before, unlocking use cases with orders of magnitude higher addressable markets, until it saturates all of physical labor.

Yes I know that is a funny looking curve. I’m being serious. When I say L-curve I really mean it.

Now let’s discuss each stage of robotics one by one.

Level 1 - Caged Industrial Arms

The arms that weld cars. They are blind, dumb, and pre-programmed, fenced off from people because they cannot perceive a human walking into the cell. The entire factory is designed around them, so every incremental robot requires designing and building another bespoke environment. That is the most expensive, least flexible form of adoption possible, which is exactly why the curve is linear and the terminal value low. The installed base is tiny despite the technology being decades old.

If you look in the market, it is clear that caged arms are not a frontier technology at all. Instead, it is an industrial appliance and grows perfectly in line with industrials. The International Federation of Robotics counts on the order of half a million new installations a year, and forecasts global installations to grow only about 7% a year through 2028, with the market value (roughly $45 billion in 2024) compounding at low double digits at best. Growth tracks manufacturing and auto capex so tightly that 2024 installations actually fell in Japan and Korea.

Conclusion: These robots are equipment and not technology.

Level 2 - Collaborative Robots (Cobots)

Cobots can sense enough to share a floor with people. The environment still bends around it, just less. Because each deployment now costs less environment, the curve steepens into a mild power law and the terminal value rises, even though the hardware is weaker than a caged arm. The inflection is arriving now.

Cobots serve the same end market but grow slightly faster due to its higher generality, resulting in a larger addressable pool of use cases within industrials. It is less mature, so it starts off a smaller base (on the order of $1 to 2 billion in 2024) and compounds at high-teens to low-twenties percent a year, several times faster than caged arms despite weaker hardware.

Level 3 - Autonomous Mobile Robots

Warehouse movers, autonomous mobile robots, self-driving vehicles, drones, quadrupeds, and even food delivery robots! Here the machine adapts to circumstances it was never built for: a self-driving car works on a road it has never seen, a quadruped walks an oil field. The environment barely changes, so this is where real robotics begins and the curve becomes a true exponential. But there is a ceiling, and naming it is the key to the whole ladder: these machines move through the world without reshaping it. They cannot manipulate their environment. That missing increment of generality is what caps Level 3.

The data takes another step up. The autonomous mobile robot market (around $4 billion in 2024) is compounding at roughly 20 to 27% a year, off an ever smaller and more immature base, and that is before you fold in robotaxis and drones, which are the same generality class. This is the first genuinely exponential robotics market as these machines adapt to existing warehouses, roads, and sites instead of demanding new ones.

Level 4 - Humanoids

This is the endgame. The robotic form factor that can replicate all of the human’s actions and fully replace physical labor.

The humanoid removes the last constraint, because it is built in the shape the entire built world was already designed for: the human body. Anywhere a person can go and act, it can go and act, so the environment needs no redesign at all. The redesign already happened, for us, over centuries.

Add manipulation, the ability to change the world and not just traverse it, and generality is complete. That is why Level 4 is the only rung shaped like an L-curve: a long flat approach, then a vertical wall.

Why is it vertical? Because for one, there is no market for humanoids today. It starts from a base of zero. And two, when you add manipulation, which is the final unit of generalization, the only difference between a robot and a human laborer is cost. For the world’s unglamorous manual labor (that humans don’t intrinsically derive enjoyment or purpose from and would much prefer to work another job) there is no reason to hire, not to hire a robot once the cost becomes lower than that of a human. Therefore, there is an economic crossing point after which, you can have a zero-to-one adoption curve.

“Analyst forecasts” are hilariously far apart: Goldman Sachs says $38 billion by 2035 (a figure it revised up sixfold in a single year), Morgan Stanley says $5 trillion by 2050. Basically, no one knows. Revenue is the wrong metric for a market that does not exist yet, and later I will argue the right metric is a capability number borrowed straight from how people forecast AI.

In conclusion, the more general the robot, the larger the addressable market, the smaller the current base, the more exponential the growth, and the more frontier-technology-like it is.

The Four Stages of AI

Now AI.

Level 1 - Pre-Programmed Expert Systems

If you’re deep enough in the AI rabbit hole, you might have heard of ELIZA.

Prior to neural networks, AI relied on expert systems, which is literally pre-written code.

Maybe some more relevant applications of expert networks are things like credit scores or insurance premiums or college admissions rubrics. This really isn’t even software. It’s literally just the concept of a decision tree. The equivalent of caged industrial arms. No one talks about them. No one cares about them. Yet they are ubiquitous and run a lot of our most important systems.

But they are not growing, they are not generalizable, and they are NOT technology.

Level 2 - Neural Networks

Have you heard of a CNN?

Convolutional neural networks were the major breakthrough in computer vision that allowed neural networks to tell the difference between cats and dogs, popularized in the 2010s.

This category also includes Google Translate and the chess engine Stockfish. They are all really good AIs! The only thing is they can only do one thing. When AI beat humans at chess, people freaked out for maybe two seconds and then didn’t gaf (give a fuck). The market didn’t gaf either. These things probably grew at the speed of the general software market and, despite being AIs, did not cause any technological acceleration or boom.

Why? Because you need to redesign you need to design the environment around the AI for the AI to work, just like you need to design the factory for industrial robots for those robots to work. For Stockfish to be the smartest human on the planet, you must give it a chessboard. For CNNs to properly classify images, you must collect labeled data.

Again, without proper generality, it is not a frontier technology with a true exponential.

Level 3 - ChatGPT

This is the first application of AI where people referred to it as a “moment.” Specifically, it was the ChatGPT moment. That’s how you know it’s a real technology with an S-curve.

This is the mobile robot equivalent because it moves. It moves not through physical space, but through domains of knowledge, from one field to another. It can do your high school close reading homework questions on The Great Gatsby then in the very same chat write you the code for a shitty SVG of a meme that you wanted to post online.

Yet it is still not able to act on the world. Exactly the reason why mobile robots are still separate from humanoids. And exactly the reason why there was still another moment ahead where the growth turned from an S-curve to an L-curve.

Level 4 - Agentic AI

Ah yes, Claude Code. The reason why SMH is up 76% YTD. It’s so useful that literally everything is in shortage.

Not an AI that answers, but an AI that does work, entering any computer and operating it. This is the humanoid of software, and the operative word is the same one that capped Level 3: manipulation. The agent manipulates the digital environment the way a humanoid manipulates the physical one, and that last increment of generality turns the S into an L.

Conclusion

We have had AI since the 1960s and genuinely useful AI since the 2010s, yet the world did not care until 2023. Why did decades of AI grow at the pace of the ordinary economy rather than like “AI”? Because Levels 1 and 2 were domain-specific, and a domain-specific technology spreads only as fast as the environments built around it, exactly like Level 1 and 2 robots. The curve bent only when generality arrived. The lesson transfers cleanly: robotics has already had its long 1960-to-2010 era, and it is about to have its 2023.

The Big Three Labs

Robotics is so AI-coded that even the big three labs are the same.

You know the AI labs, OpenAI, Anthropic, and Google. But what about the robotics labs?

…FigureAI, Apptronik, and Tesla!

They match one for one, do you see the resemblance?

…no?

Figure is (early) OpenAI. The “posterchild” pure-play private that has the highest valuation ($39b) and is “in the lead.” Both their names even end with AI!

They have a backer list (Microsoft, Nvidia, OpenAI, Jeff Bezos) that reads like OpenAI’s own cap table. If you have watched Brett Adcock say at least three words, you will understand that their entire ethos is we are the leader and no one is close. They are fully vertically integrated and have the Apple approach: building both the hardware and its own AI models (its Helix system, no reliance on an outside model vendor), and it was first to ship to a paying customer, BMW, back in 2024. It talks in maximalist terms, 100,000 robots over four years, a path to being one of the most valuable companies on earth. Figure is the maxi poster child, and like OpenAI it draws both the most hype and the most “they are promising way too much” skepticism. But if you think back to the OpenAI spending commitments (and ORCL chart manipulation), when you’re the maxi, people think you’re crazy at first until you get proven right, so this company might just be a fantastic bet.

Apptronik is Anthropic. The names literally rhyme. They are the pragmatic and heads-down-execution focused counterpart to Figure. They are valued way lower at $5b.

Its founders are openly disciplined and anti-hype, and they will more or less tell you the other guys are taking advantage of irrational exuberance and “not doing the work.” Strategy-wise Apptronik is the Android of the space: more modular, more model-agnostic, a platform play rather than a single sealed product. It partners with Google DeepMind for the AI model (DeepMind’s largest-ever investment) while owning the hardware, the platform, and the data flywheel.

Tesla is Google. This is self-explanatory as they are both Mag7 companies with a frontier lab division (Optimus for Tesla, Deepmind for Google).

Just like Google, they are vertically integrated in a way that the labs cannot be. The labs can be vertically integrated, but as a mega cap, you can be hyper vertically integrated: the robot, the factories, its own TPU edge chip (AI5), the batteries, the AI training stack, and, critically, its own first customer, since the first place Optimus has to earn its keep is inside Tesla’s own factories. This probably means a lower risk for initial deployments and a big data advantage. To push this Google parallel thing further, it’s like deploying Gemini across the entire Google ecosystem. So yeah the Google of Hardware.

Then there is of course Unitree (China) which is DeepSeek with the exception that they are already a behemoth. They have by far the lowest cost structure with a BOM 1/3 of that of western leaders and offering their flagship H1 at $16k. This is simply due to them being within ten miles of all their suppliers, unlike the West, which has to import parts from Germany and Japan. This works great for semiconductors, where niching down is an asset and talent is spread across the world (because quality and pushing the frontier is paramount), but in robotics it’s actually iteration time and cost structures that are most important.

But unlike with AI, there is no open sourcing. Western markets will ban Chinese robots. So the Western market will be divvied up by the leading Western labs. I do not believe Unitree will participate.

The Elbow of The L-Curve

This is an L-curve. The elbow is what the person is standing on (and I’ve circled it too).

Definitionally, when I say something has an L-curve, it must mean that I expect there to be an “elbow moment” when it turns from flat to vertical. In agentic AI the elbow was Claude Code and we reached it earlier this year.

So what is the elbow for humanoid robotics? And when do we reach it? I believe there is one answer.

When it is cheaper to hire robots than humans to perform repetitive, fixed-station, load-bearing manual labor.

There are several things that I am saying with this one sentence.

1. Cheaper. This means that we must analyze the cost structure of humanoid robots.

2. I only define one category of tasks. This means I implicitly believe that repetitive fixation load-bearing manual labor is THE use case sufficient to reach the elbow.

Let’s focus on the price first.

The price dynamic is less prominent for AI and knowledge work just because knowledge work is much more quality-focused than cost-focused. The takeoff moment for AI has always been caused by capability and not price. Think about it. The METR time horizon chart measures the longest task an AI can perform, NOT how cheaply it can perform a certain task.

This is structural. Think about it. Token generation is orders of magnitude faster than human writing. When working with bits, it’s only natural that the virtual-native entity wins in speed and efficiency. The only question is whether it can match a human’s original thought quality.

However, in the physical world, nothing innately makes a robot faster than a human, as they are bound to the same laws of physics that we are. Therefore, you could probably get a robot to perform any task today with enough point training, task-specific RL, completion time, patience, and teleoperation. The only difference would be cost. Therefore, the robotic equivalent of the METR time horizon chart is an hourly labor cost index, like this excellent one provided by SemiAnalysis.

In order for robots to cross the cost threshold, the all-in price of a robot (purchase price per hour of useful life + expected cost of maintenance + expected human teleoperation time + expected cost of quality/reliability) must be lower than the all-in price of a human (hourly wage + taxes, medicare, social security). The all-in cost of a robot is usually not itemized like this from the perspective of the end consumer, as it is usually wrapped into a robot-as-a-service (RaaS) contract. Also, by using hours, I am ignoring the idea that robots don’t get injured, sick, or tired and can work double shifts, because that is just calculated into the purchase price per hour of useful life by extending the useful-life-hours.

Let’s make this nice and mathematical.

for a specific task, r = (robot $/hour) / (human $/hour)

r > 1, hire some dude. r < 1, use a RaaS. When r falls below 1 on a task that is a large share of the economy, the elbow has arrived.

Now actually run the numbers. How far are we?

Figure leases its robot at around $100,000 a year, and experts describe a real deployment today as something like a $50,000 robot plus six figures of onsite integration plus a human minder to babysit it. Amortize the hardware, add a teleoperator who can supervise only a few robots, and account for low uptime and rework, and a robot’s all-in cost today lands somewhere around $85 per productive hour, against a human line of $15 to $30. So today’s r is roughly 3 to 6x.

Robots are not close, which is why current deployments are really subsidized pilots and data-collection exercises, not real business. But it’s not an order of magnitude off!

But look where the cost is. The sticker price is already near parity: a $100,000-a-year robot that runs two or three shifts is competing with two or three human workers, so the hardware alone is only slightly above the line. The thing keeping r at 3 to 6x is the teleoperation and reliability. That is the entire game. The crossing does not require a cheaper robot so much as a robot that needs far less babysitting and runs far more of the day. When autonomy rises enough that one supervisor covers fifteen robots instead of three, and uptime climbs toward multi-shift, the all-in number collapses toward $10 per productive hour and r drops below 1.

Moravec’s Paradox

In my definition of the elbow, I only defined one category of tasks. Now we will discuss why.

I believe for AI, there was one use case and one use case only which helped us achieve economic takeoff: coding. It was a task that is large enough in the economy and the first for automation to reliably outperform humans. I call a task this set of attributes a critical task.

To grok the nature of a critical task on a much deeper level, let’s visit a concept known as Moravec’s Paradox.

In the 1980s Hans Moravec, Rodney Brooks, and Marvin Minsky noticed something strange about AI: it is comparatively easy to give a computer adult-level performance on intelligence tests or chess, and almost impossible to give it the perception and mobility of a one-year-old. The explanation is evolution. The longer natural selection has worked on a skill, the more deeply optimized and the harder to reverse-engineer it is. As Moravec put it, encoded in the sensory and motor parts of the human brain is “a billion years of experience about the nature of the world,” while “abstract thought is a new trick, perhaps less than 100 thousand years old.” This yields the master ordering rule for the whole automation wave: machines conquer human tasks in roughly the reverse order of how long evolution spent building them. Evolutionarily recent skills, symbolic, abstract, structured, fall first; evolutionarily ancient skills, perception, dexterity, locomotion, social reading, fall last.

It is these evolutionarily recent skills, specifically the ones that matter for the economy, that are candidates for being a critical task.

Now let’s look coding’s fundamental attributes.

1. Data rich. The corpus already existed. BigCode’s “The Stack” assembled over 6TB of permissively licensed source code across 358 programming languages, roughly 900 billion tokens in its second version, scraped from public GitHub. Decades of human code were sitting there, labeled and ready, the way no physical-action corpus is.

2. Verifiable. Code compiles and runs, or it does not. That objective, automatic signal is what let reinforcement learning with verifiable rewards work on code and math when it stalls elsewhere: the reward comes from a compiler or unit test, it is binary and bias-free, and the model cannot easily hack it. A clean reward is a cheat code for machine learning, and code hands you one for free.

3. Evolutionarily novel, therefore scarce and highly paid. Programming is so recent that the brain has no dedicated machinery for it. An MIT study found that reading code does not recruit the brain’s language network at all, it lights up the general-purpose “multiple demand” network, and the authors note that “computer programming is such a new invention that there couldn’t be any hardwired mechanisms that make us good programmers.” So competent programmers are rare and expensive.

   1. Instead, human brains are optimized for social intelligence. Social interaction is inherently far more complex than writing a few lines of code. Yet our brains handle every micro input subconsciously, without us even having to notice it.

TLDR: Hard for us, useful for the economy, easy for a machine? Automate it.

So now let’s translate this to our physical bodies. What is the physical equivalent of coding, and what is the physical equivalent of social intelligence?

The body’s equivalent of social intelligence is endurance running. Humans are the best endurance runners in the animal kingdom, a capability that emerged about two million years ago in the genus Homo, with spring-like tendons, an upright gait, and, above all, a cooling system without peer: two to four million eccrine sweat glands spread over nearly hairless skin, giving humans the best evaporative thermoregulation of any primate and the ability to run prey to heat exhaustion in the midday sun, a tactic called persistence hunting. We can also add precision dexterity to the mix, as our hands have dozens of degrees of freedom and our senses are hyper-tuned to its positioning.

(As they always say, it is sweating and opposable thumbs that let humans take over the world.)

The body’s equivalent of coding is factory work. Evolution optimized the body for varied, intermittent movement, not for repetition or sustained static load. The assembly line is barely a century old, Ford put it together in 1913, and the body has no adaptation for performing the same motion thousands of times a shift or holding a loaded posture for eight hours. So it breaks, measurably and expensively. Overexertion and musculoskeletal disorders are roughly 30% or more of all US workplace injuries, transportation and warehousing carry the highest serious-injury rate of any major sector, and over a million Americans suffer serious back injuries each year (US BLS). Overexertion from lifting, carrying, pushing, and pulling is the single most expensive category of serious workplace injury, about $13.7 billion a year in direct US costs, the bulk of it manual material handling (Liberty Mutual Workplace Safety Index, 2024). That injury bill is the body “hating” the task, the precise physical analogue of the brain hating symbolic logic.

We have our answer. The critical task, the “coding” of robotics is repetitive, fixed-station, load-bearing manual labor. Machine tending, parts and package handling, palletizing, sorting, kitting, repetitive insertion and assembly. It clears all three bars at once, for the same reasons coding did.

In addition, factory work is pretty big and important to the economy if you ask me. This is why the first customers of these humanoid startups are all car factories.

Finally, let’s look at the other side. The last physical tasks to fall are the body’s social-intelligence equivalents: dexterous, varied, unstructured, socially embedded work, the nurse’s touch, the chef in a chaotic kitchen, and childcare. High evolutionary investment, high Moravec tax, low data, low verifiability, deeply social. That bundle is the robotics version of humor, and it is the part of physical labor that stays human longest. The same evolutionary moat that protects the social parts of white-collar work protects the dexterous, caring, and improvisational parts of physical work.

The Economic Singularity

What happens once the elbow’s reached and the critical task is automated? Well, my friends, I introduce you to the concept of economic singularity.

Economic singularity: the state in which a technology is so cheap and so useful that no actor retains the agency to stop its development, because demand alone now forces it forward.

It is not necessary for a technology to be in the economic singularity state for a huge build out to occur. Take AI in 2023 and 2024. Hundreds of billions were being poured into capex while the bears argued that there is no way chatbot subscriptions can pay for all of it, and I agree! But that doesn’t mean the build-out has to stop. It just meant that its continued development was contingent on the decisions of the parties funding the development. You could have stopped it by convincing Satya Nadella, Andy Jassy, and Sundar Pichai to halt AI capex.

I believe the economic singularity has occurred (or more accurately, an economic event horizon, a point of no return) when demand alone is sufficient to drive continued development. The reason why this is a “point of no return” and not simply a temporary supply-demand imbalance is that, theoretically speaking, the marginal utility of a general-purpose automation technology like AI or robotics never flattens out, similar to the marginal utility of money itself, as it can be traded for any other good or service. Smartphones saturate when everyone owns one, but here, the TAM is GDP itself.

This is what happened with Claude code. Now you can convince those same three CEOs to stop tomorrow and nothing changes, because demand is so overwhelming that someone else simply spends to meet it. Capability is now sufficient to ensure AI’s own continuation. Development left the agency of any company and passed to the market. That is the singularity: capitalism, not a boardroom, drives it.

This is what will happen to robotics once r < 1.

Today humanoid R&D is a discretionary bet placed by a few well-capitalized companies. Development contingent on their agency. Once the critical task crosses r below 1, Level 4 hits the elbow: buyers demand robots faster than anyone chooses to build them, demand becomes the driver, and production becomes self-pulling.

Robotic Self-Improvement (RSI)

It’s recursive self-improvement… but robots. Robotic Self-Improvement!

Recursive self-improvement is simple. An AI good enough to do AI research designs a better AI, which designs a better one, and capability compounds with no human in the loop. That is the digital singularity.

Robotic self-improvement is the same loop in the physical domain. A humanoid general enough to build robots and to build and run the factories that build robots closes a physical cycle: robots staff the lines that produce robots, which build the factories that produce more robots. They multiply like bacteria.

This is the end game. I believe we are likely to reach RSI for AI before RSI for robots, just because AI development is approximately 4 years ahead. However, once you have both, you have reached the ability to automate every single part of the economy.

They feed back on each other too. Better AGIs design better robots to speed up robot production even more and better robot neural nets to make them smarter, while robots build better fabs and datacenters to feed the AGIs. Double infinite recursion.

This is infinite GDP.

Conclusion: Predicting ChatGPT and Claude Code Moments

There are two robotics inflection points to try to predict:

1. The ChatGPT moment, which is when level 3 reaches the inflection point of its S-curve

2. The Claude Code moment, which is when level 4 reaches the elbow of its L-curve

I believe we’re in the robotics equivalent of AI’s 2022. The ChatGPT moment is likely just around the corner while the Claude Code moment is ~4 years away. This puts robotics at a development stage roughly 4 years behind AI.

The robotics ChatGPT moment: 2026 to 2028, just beginning now. This is Level 3 taking off, the first real exponential, mobile and perceptive machines crossing into broad use. We have not quite had it yet, but 2026 is where the inflection starts to show. Here we want to track the KPIs, like miles driven, revenues, number of deployments, and whatnot. There are many tasks and forms of robots (unlike level 4 and humanoids) so the correct measure is an aggregate of many measures. For example, autonomous mobile robots are compounding north of 20% a year, and robotaxis are growing pretty quickly: Waymo went from about 250,000 paid rides a week in early 2025 to roughly 450,000 to 500,000 by early 2026, doubling in under a year, with a stated path past one million a week by the end of 2026. Tesla is not doing bad either. We are honestly almost there; all that has to happen is for the public to start becoming enamored with one of these products, and I think there’s a solid chance it happens in 2027.

The robotics Claude Code moment: 2029 to 2031. This is Level 4 humanoids hitting the elbow, the critical task crossing r below 1, and the economic singularity engaging. Here revenue is useless, because there is none, exactly as there was no “coding revenue” to extrapolate before agents arrived. So borrow the trick that actually worked for AI. METR measured AI capability as a task time horizon, the length of task (in human time) a model can finish at 50% reliability, and showed it doubling roughly every seven months, an extrapolation that has tracked reality really damn well and let people call the agent inflection before it happened.

The robotics analog is the cost horizon on factory labor.

This is illustrative, but I believe a chart like this is going to become the robotics equivalent of the METR time horizon chart for AI, religiously tracked on X to answer the question of whether scaling laws are intact. If we assume that robotics costs decline in line with Moore’s Law (i.e., a halving every two years), then we will reach the elbow in 2030. If we assume that robotics development is four years behind AI and the robotics Claude Code moment happens 4 years after the AI Claude Code moment, which was 2026, then we also land at 2030. Therefore, 2029-2031 is my current timeline.

Now for closing thoughts. As investors, we are blessed. We have watched the first General Purpose Automation Technology take off, and through empirical observations, we have understood every stage of its inflection. Today, we sit at the precipice of the takeoff for the second. Robotics’ attributes are fundamentally analogous to what we observed and understood about AI, allowing investors to make predictions with far higher confidence than betting the farm on AI infra back in 2022.

Yet the world (and the market) doesn’t see it because it’s not yet “in your face.” That is our opportunity.

Luckily the free section still exists on X. Press F to pay respects to the paid section.

If you’ve been struggling to value NeoClouds or even think about them clearly and have figured out that they’re different from other businesses but don’t know why, do not worry (I figured it out)

Why NeoClouds Break Normal Valuation

Most companies are valued on what they already are. A memory company is a bet on book value through a cycle. Nvidia or TSMC is a bet on earnings: a durable moat that earns and grows profit as the market grows. Crucially, these businesses do not need to raise capital. Even the capital-intensive ones fund growth out of operating cash flow; the occasional debt or equity raise is a one-off, not the engine. Nvidia never has to raise capital. Micron never has to.

NeoClouds are the opposite. Raising capital is not incidental to the model; it IS the model. Annual capex runs at a large fraction of, and sometimes the entirety of, the company’s market cap, every year, while revenue grows just as fast. That breaks both standard lenses at once. Forward multiples stop meaning anything because the denominator is exploding. Price-to-book stops working because book value is unstable because it’s being rebuilt every quarter by fresh capital, and the price itself is unstable because enterprise value is constantly inflated by new debt and dilution. The equity is a moving target sitting on top of a balance sheet that is a moving target.

What you are actually holding is a corporate wrapper for raising capital and deploying it into compute. Once you see it that way, the right valuation lens falls out.

Spread

A NeoCloud takes money from debt and equity investors and invests it in GPUs and data centers, exactly as a bank takes money from depositors and invests it in assets. The value it creates is the spread between its cost of capital and its return on that capital, and the equity is worth the present value of that spread, compounded over everything it will ever deploy.

This is how the operators themselves underwrite it: a mid-to-high-teens unlevered IRR on compute investments over roughly the ~5-year life a GPU is depreciated to. A high-teens IRR simply means the contract price on that GPU is high enough above the all-in cost of the GPU to clear that return. So the entire bull-vs.-bear question collapses to one thing: is there a durable spread between return on capital and cost of capital, and is it widening or compressing?

Why Would a Spread Exist?

The bear case is clean: NeoClouds are middlemen who buy compute and resell it. If that is all they do, customers hold the pricing power and compete the contract price down until return on capital equals cost of capital, and the spread goes to zero. The bull case is that the spread is real and persistent. There are four sources of it: two genuine value-adds (durable), and two commodity-cycle dynamics (positioning):

1. Product / operating excellence (value-add). Being genuinely good at running a cloud, with software, orchestration, and API services on top of the raw metal. A better product commands premium pricing, which widens the spread directly.

2. The people (value-add). What a customer is really buying is the operator’s team. Its relationships with Nvidia, the OEMs, and the rest of the supply chain, plus a track record of delivering, are far stronger than any relationship the customer could build on its own. You are buying that team’s relationship with the suppliers, and the certainty that they will turn scarce silicon into delivered, on-time compute. That certainty commands a premium.

3. Allocation scarcity (commodity). In a shortage, access to Nvidia allocation is itself the scarce good. You pay the NeoCloud to get in line, economically identical to paying fees into an SPV to access an allocation in a hot private company.

4. Performance surplus (commodity / market inefficiency). Each Nvidia generation improves performance by roughly an order of magnitude, but Nvidia cannot raise price by an order of magnitude. That would invite antitrust scrutiny and customer revolt, so it passes much of that surplus downstream. NeoClouds are first in line to receive it. Everyone in the chain captures a slice, but the first recipient can take the most disproportionate share. The present value of that inefficiency lands straight in the IRR.

The first two are moats you build. The last two are a function of being in the right place at the right time in the cycle. Today all four are live, which is why the IRR is high-teens while the cost of capital is nowhere near it.

Growth IS Intrinsic Value

Here is the part that makes NeoClouds strange. Because the IRR sits well above the cost of capital, every dollar deployed is a positive-NPV project. And demand is not the constraint; it is effectively infinite. Operators will tell you that a fresh 500 MW would sell instantly. So the business is not gated by how much it can sell. It is gated by how much capital it can deploy and how fast it can build.

That inverts the usual logic. For a normal company, growth is good only if it earns above its cost of capital on incremental investment, and it is usually demand-limited. For a NeoCloud in a shortage, incremental deployment is reliably positive-NPV and supply-limited, so more deployment is simply more value. The equity is worth the present value of the spread on all the capital it will ever put to work. This is why a NeoCloud can trade at a “ridiculous” price-to-book or price-to-earnings and still be cheap: if the market is not pricing in that the company will grow its compute base by an order of magnitude, the present value of the spread on that growth can dwarf the current, supposedly-overvalued, equity value.

Enterprise value is the present value of future positive NPV projects, not just future cash flows!

What Makes a Good NeoCloud

It follows directly. There are four ways to be a good NeoCloud: two that widen the spread, and two that let you deploy more positive-NPV capital.

Widen The Spread

1. Build a great product. A real cloud and software/API layer earns premium pricing.

2. The people. A NeoCloud’s supplier relationships, credibility, and track record live in its team. A customer is buying that team and its relationship with the suppliers, stronger than its own, and pays a premium for the certainty it provides. This is what separates it from lever 4. Here, it is the relationship and credibility that earn pricing, not raw build throughput.

Deploy More Capital

3. Capital access and cost of capital. Raising quickly, at good prices, and lowering the cost of capital both widens the spread and removes capital as a growth constraint.

4. Construction and execution speed. Power access, building data centers faster than anyone else, and hiring and operating at scale. This is the most important lever, precisely because demand is infinite; the binding constraint is how fast you can physically build.

A bad NeoCloud is a pure commodity middleman: thin or no product, ordinary execution, and expensive or constrained capital. Its spread compresses toward its cost of capital and its growth stalls, so it has neither a wide spread nor a large base to apply it to.

The best operators combine all four levers: a genuine product and the right people to widen the spread, plus cheap, abundant capital and construction speed to deploy it. There is also more than one way to win: an operator can lean on product and software differentiation, or on raw scale, allocation, and a relentless capital-markets engine. What they share is the ability to compound a wide spread across a rapidly growing compute base faster than the market underwrites.

The Investment Translation

Don’t value a NeoCloud on a forward multiple or on book. Both are unstable by construction. Value it as the present value of the spread between return on capital and cost of capital, applied to all the capital it can deploy. Two questions decide everything: Can it sustain the spread? (product + people/relationship moats, against the bear case that customers compete it away) and Can it keep deploying? (capital access + construction speed, against a world where demand is never the limit). The best and most underpriced NeoClouds are the ones that compound a wide spread across an order-of-magnitude-larger compute base, faster than the market is willing to underwrite.

To be clear, believing in an Indium Phosphide shortage is different from just being bullish on optics broadly.

Optics is an end market. Indium Phosphide is a material input.

The intensity of the material usage in the end market can either go up or down. In addition, there are also supply dynamics. Demand could go to the moon but there is no shortage if supply goes to Mars.

There are also many layers to the Indium Phosphide supply chain, as I cover in this piece:

• Indium Phosphide substrate

• MOCVD/Epitaxy machines

• Laser device fabrication

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CPO Supply Chain 101

The most important concept to understand when analyzing the CPO supply chain is the power of e x p o n e n t i a l…

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Some of which will be in much greater shortage than others.

The key to… bottleneck investing (sigh) is to figure out which layer controls the gating input to the final unit produced. It could be the upstream most layer, downstream most layer, or anything in between. There is a common perception that the more upstream something is, the more of a bottleneck it is, but that relationship is not necessary.

Our agenda today is simple. We start by highlighting why Indium Phosphide demand is going hyper-exponential beyond EMLs and regular commodity CWs powered by two main products:

• Ultra-high power CW lasers for CPO

• Indium Phosphide PICs

Then, we’ll build supply and demand models for all three layers of the stack: indium phosphide substrates, MOCVD machines, and laser devices.

Finally, we’ll finish with how this translates into the financials for the most important company in each layer.

Contents

1. Ultra-High-Power CW Lasers for CPO

2. Indium Phosphide PICs

3. InP Substrate Demand Build

4. InP Substrate Supply Build

5. MOCVD Tools Supply/Demand Model

6. InP Device Supply/Demand Model

SemiAnalysis Giveaway: The first person to subscribe using the paywall on this post will be selected to receive one free month of SemiAnalysis (sent to your email).

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

Ultra-High-Power CW Lasers for CPO

UHP CPO lasers are a topic that I’ve covered extensively. So much so that you are probably tired of me talking about it. Welcome to my nth laser lecture.

There are two types of lasers:

1. Vertical-Cavity Surface-Emitting Lasers (VCSELs, pronounced vik-sel) emit light from vertically… from a cavity… on the surface. They use GaAs, aren’t great for long reach because they can’t emit O band light, and fail at higher data rates

2. Distributed Feedback (DFB) lasers emits light horizontally through a bunch of tiny mirrors that bounce it in a feedback loop to get a really concentrated and clean beam. They use indium phosphide! These are the primary CPO lasers.

For CPO, the DFB light source must be remote for the purpose of avoiding heat and maintaining serviceability.

The only way to ensure that the light survives the coupling loss from this journey is to make it high power.

Why not multiple lasers instead? To maintain signal integrity, the light traveling from the laser to the optical engine has to stay in a consistent orientation — consistent polarization. This means every laser requires polarization-maintaining fiber, which is expensive, and the process of attaching it is painstaking and yield-sensitive. We must minimize the number of PM fiber connections per system at all cost, which means using only one laser.

These lasers are also continuous wave (CW). DFBs can either be CW or EML.

CW lasers are lasers that just stay on. It produces a continuous stream of light, like a light bulb or flashlight. A CW laser can provide a steady beam that gets modulated (gets the signal put into it) somewhere else.

EMLs (electro-absorption modulated laser) are lasers plus a built-in light switch. EML stands for electro-absorption modulated laser. The laser creates the light, and an attached modulator rapidly changes that light on/off or high/low to encode data.

Die Sizes

Now comes the fun part: die size estimation. We know that the three main types of lasers used for optical data center optical communication are

1. Low power CWs (30-70mW, used in Sipho 1.6T transceivers)

2. EML (used in all sorts of transceivers)

3. Ultra high power CW (400mW+, for CPO)

So to gauge demand for InP, it’s time to ask: how much Indium Phosphide does each type of laser actually require?

Our base unit will be the 100G EML because it ships in the most volume today. This is the optical equivalent of Toyota Corollas or Big Macs. Or football fields.

EMLs are very low power, even lower power than low power CWs. However, they have a built-in modulator. Therefore, low power CWs are smaller than 100G EMLs.

200G EMLs are obviously larger than 100G EMLs.

Ultra high power CW lasers on the other hand, are MASSIVE. You need a physically larger gain region to generate all of that light. This makes it 5-10x larger than a 100G EML.

This massive die area consumption is what makes UHP CWs an order of magnitude more InP heavy than existing products on the market. They are the first of our two InP demand drivers.

Indium Phosphide PICs

The second InP demand driver is Indium Phosphide PICs. These are not as widely discussed as ultra-high power CWs, so let’s take a moment to understand what they are and why they are needed.

Optical communication is simply transmitting data through light. There are two ways to encode data in light (known as modulation): IMDD and coherent (no not the company).

IMDD is basically flashing a flashlight on and off. Only encoding signals in brightness.

Coherent modulation is like having one of these:

It encodes signals in brightness, phase, and amplitude.

The benefit of coherent modulation is that it makes it much easier for the receiver to detect the signal, therefore allowing the it to survive a greater insertion loss (higher link budget). This is why coherent is used for long-reach telecom and scale across.

On the other hand, it is much more expensive and complicated, as you can imagine.

Scale-out in the data center is now running into the limits of IMDD’s link budget. This is because:

1. The links are too long

2. Optical circuit switching (OCS) is being adopted. Each time light passes through an OCS, it loses 1.5 to 3 dB of signal.

Therefore, scale-out is moving to adopt a light version of Coherent known as Coherent-Lite (Yes i know it sounds like a Coherent and Lumentum merger. Who named these modulation schemes?).

Coherent light modulation requires a far more complex optical device (InP PIC) than IMDD. It makes a 100g EML look like a 2x4 Lego brick.

All of this extra stuff is to modulate phase and amplitude.

Note that not all of this is Indium Phosphide. You can have some parts of it be silicon photonics, which makes it a lot cheaper. The standard version, which has the transmit on InP and receive on SiPho, has a substrate consumption intensity of approximately 100x that of 100G EMLs. This is what we’ll be using for our models.

InP Substrate Demand Build

Next, I will share my supply and demand models for:

• indium phosphide substrates (AXTI)

• MOCVD tools (Aixtron)

• indium phosphide devices (Lumentum, Coherent, Nokia, etc.)

We start with an overall demand build for 4-inch indium phosphide wafers that informs every model.

We’ll look at some pretty charts that show the equilibrium balance/imbalance intuitively. The numbers from every use case (demand) and every supplier (supply) shall be color coded. My research is really lit.

The metric unit of measure for indium phosphide demand today will be 4-inch wafers. This can be used to measure everything from substrate demand to epitaxy demand to final device demand. But this chart below is substrate-specific. You’ll see why this is important later.

If you didn’t grok the implications of the wafer area intensity numbers from the previous two sections, hopefully this graph shows you just how insane it is. All of the transceiver lasers are minuscule compared to ultra-high power CWs and Indium Phosphide PICs.

From 2026 to 2030, the total demand CAGR is 56%, increasing by nearly 6x, driven entirely by the two new use cases, UHP CW and InP PIC, which together contribute 6x more content than traditional transceivers by 2030.

But also observe that non-AI uses for InP still take up a big chunk of the demand. This means that even with gangbusters growth, AI is starting from a smaller base than many think. This is important for the substrate market, not so much for epitaxy or device fabricators, as they are much more AI-focused and don’t touch the telecom end market as much.

InP Substrate Supply Build

Substrates are our first supply build.

For more context on the three layers of the indium phosphide supply chain that we’ll be analyzing the supply of today, please read this article. It is my most popular article and is required reading.

Jason's Chips

CPO Supply Chain 101

The most important concept to understand when analyzing the CPO supply chain is the power of e x p o n e n t i a l…

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4 months ago · 127 likes · 15 comments · Jason's Chips

The results for our first look at supply might actually surprise you and not in the way you expect.

Interesting. Demand actually never fully exceeds supply? And it doesn’t even get close to announced nameplate, which is simply a measure for the aggregate supply ambitions of all substrate vendors, not how much they are actually likely to bring online.

The answer is there is a China problem. Particularly in substrate capacity, as once you are actually competent, it is quick to bring online.

One Chinese firm, Yunnan Germanium, will make up nearly half of all Indium Phosphide production by 2030. However, this is even a conservative estimate of their capacity, as they have publicly committed to 450k of 4-inch equivalent wafer supply, and our 2030 full ramp is only 250-300k, to add a buffer for export controls and qualifications.

As a result, despite explosive demand, supply never really becomes tight. This is obviously bad for AXTI. In a way, it is kind of the opposite of memory, which is a market with much more modest demand growth but extremely inelastic supply, as it takes years to bring on a new fab and is much more capital intensive. The market structure of memory, despite lower demand, is perfectly ripe for a massive shortage. Indium Phosphide substrates, despite having much faster demand growth, is not.

This teaches us an important lesson: the bottleneck is not always the upstream-most component. A shortage could, in fact, be somewhere in the middle of the supply chain if the upstream inputs are abundant and the scarce “magic” is added after the fact. Now let’s look at this scarce middle.

MOCVD Tools Supply/Demand Model

The MOCVD tool market is literally only Aixtron.

If you listen to enough earnings calls, you will know their capacity forecasts are approximately 1 billion in total revenue per year or 240 tools per year. However, this capacity is expandable. They are currently working a one-shift model, but they can instead work two shifts or weekends if demand necessitates, leading to higher effective capacity. In addition, they’re building a brownfield plant in Italy and a greenfield plant in Southeast Asia, which expands their capacity to 300 (after the brownfield plant) and even higher (after greenfield).

So the supply curve ends up looking something like this. However, not all those tools will be available for Indium Phosphide. Aixtron has a big power semi business, which will likely inflect with the advent of 800 VDC.

But notice demand is actually overwhelming enough that my model shows we will shift into a shortage by 2028! How come we will be short MOCVD machines but not substrates?

The simplest explanation is to blame it on China, but there’s actually a clever structural logic here that I figured out because I am a genius. Currently, MOCVD tools being shipped are all new shipments specifically for Datacom. Every incremental tool shipped is needed because of data center lasers — there is an existing installed base that produces legacy telecom devices which aren’t compatible with these new datacom lasers.

However, because substrates are a flow rather than a stock, the non-data-center shipments recur every year. This is why the “other InP uses” bar in our very first demand chart is so much bigger than the EMLs and CWs for data centers.

This means that demand quintupling matters way more for total MOCVD tool demand than total substrate demand as the base that you are quintupling is pretty much the entire pie rather than just a tiny slice of that pie.

InP Device Supply/Demand Model

Finally, let’s talk about InP devices. This is your Lumentum, Coherent, Nokia, etc.

This is a bit different because not all devices have fungible capacity. A fab qualified for ordinary EMLs cannot immediately pivot to making ultra-high-power CW lasers or InP PICs and vice versa.

Which results in the obvious outcome: some products can be in massive shortage while others are in crazy over-supply.

The Indium Phosphide PICs capacity is dominated by Nokia’s San Jose Fab. Nokia has by far the highest amount of capacity for this component (8 / 55 / 110 / 175 k wafers for 2027–2030). Coherent is a fast follower, ramping to 55k wafers with their 6 inch process. If demand for coherent light transceivers surprises to the upside, it is Nokia that wins disproportionately (alongside Marvell who supplies DSPs.

And yes, ultra-high-power CWs are, by far, the component that will be the most short. The mechanism is pretty simple: these are probably the hardest type of lasers to make, so the qualification process is brutal. Currently, only Lumentum has lasers that can meet the very demanding bar.

In addition, others may be able to qualify, but if their process quality isn’t nearly perfect, they can only achieve the right specs by enlarging the die size and thus reducing output. It is a brutal (very attractive) market.

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A lot of people enjoyed it so I will be copying the format one for one because I am very uncreative.

Introduction

An OCS is just a mirror box. Light goes in, bounces off mirrors (or other stuff), then goes out in a separate direction.

The most important concept to understand when analyzing the OCS market is the power of a t t a c h r a t e.

The switch itself has a bunch of ports. Higher port count is referred to as higher radix.

Now the unit of measure for OCS shipments isn’t the number of boxes because boxes can vary in size. Big boxes cost more, small boxes cost less. Instead, it is the number of ports as the cost of a box generally scales with its port count.

Attach rate can therefore be defined as the rate at which ports are attached to XPUs. 2:1 means 2 OCS ports for every accelerator chip.

And for every OCS use case, the attach rate is rising.

On top of that, OCS itself is a new technology that is in the early-mid stage of its S-curve.

Therefore, this is an excellent market because its growth rate scales with three vectors: AI growth, adoption rate, and attach rate.

OCS growth rate = AI growth * adoption rate * attach rate

Contents

1. Switch Primer

2. OCS vs Electronic Packet Switch (EPS)

3. Spine Switch Replacement

4. Google TPU Superpod OCS

5. Scale-Up OCS

6. Types of OCS

7. OCS Market Model

8. Lumentum

9. Coherent

10. Hidden Small-Cap OCS Vendor

11. Final Thoughts: Better Than CPO?

SemiAnalysis Giveaway: The first person to subscribe using the paywall on this post will be selected to receive one free month of SemiAnalysis (sent to your email).

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

Switch Primer

A switch is very simple.

Data centers must be organized in a hierarchical pattern otherwise every GPU has to talk to every other GPU which means links scale at O(n^2) which would fill up the entire data center with wires pretty quickly which is generally considered to be not good.

In order to form this network, traffic must be routed, and it is switches that route the traffic.

OCS vs Electronic Packet Switch (EPS)

An Earnings Per Share (EPS) (lol) is the standard electrical switch that is currently used almost everywhere.

It receives an optical signal as an input via transceiver, converts it to an electrical signal, reads and routes that signal via switch ASIC (logic chip), converts it back to an optical signal via transceiver, and sends it to its destination.

An OCS, on the other hand, just bounces the light off of a mirror.

So think about intuitively what the trade-offs are.

If you have to convert a signal from optical to electrical and back to optical (OEO), that certainly takes time. It also takes energy. The switch itself is also active, which takes even more energy. So generally the big problems with an EPS are latency and power.

It’s not like this is a small difference btw. OCS is practically free compared to an EPS. Lumentum on their R300 switch:

The R300 has demonstrated 98% reduction in switch latency vs. an OEO packet switch solution.

The power requirements of OCS is also less than 10% of an EPS.

But obviously an EPS is better in certain ways. Otherwise, why is it the most widely used solution?

Think about what happens when the signal exits the switch system via transceiver. It gets received, then re-sent, meaning that the signal coming out the other side is a fresh beam of light. On the other hand, in OCS, the light bounces off the mirror and loses a bit of signal and isn’t re-amplified again.

In addition, intuitively speaking, the light also has to travel twice the distance because it never gets to stop at the switch. Think of it like taking a direct flight instead of a layover.

As a result the signal suffers more insertion loss which means that when the signal finally arrives at its end destination it is a lot more mangled. Specifically, if the insertion loss from distance (in EPS setup) is x and the switching loss is y, the total OCS insertion loss is 2x + y.

The other tradeoff is that moving mirrors to redirect connections takes time. Not that much time, only milliseconds. But EPS can make fresh routing decisions for every single packet. This is the problem behind the core reason OCS was not a thing before AI, which I will lay out for you now:

Traditional cloud traffic is mouse flows.

These are tiny, short-lived, and unpredictable connections (a search query and API call, a checkout). You need a switch to actually make decisions for every packet. The connections change too fast for those micro mirrors to handle.

AI workloads are elephant flows.

Training points the same exact clusters of accelerators to each other and leaves the connections alone for hours.

OCS bears would say that as we move to inference, we move back from elephant flows to mouse flows, as each individual user query is distinct. This may be true at the leaf level. However, at the spine level (where OCS sits), the network traffic is still classified as elephant flows, as the only data that passes is prefill to decode KV transfer and not the individual tokens.

Spine Switch Replacement

Now, let’s talk mirror box use cases. There are three of note that we will discuss today:

1. Spine switch replacement

2. Google TPU Superpod OCS

3. Scale-up OCS

Spine switch replacement refers to the replacement of the spine switch.

This is the perfect (and generally the canonical) use case for OCS. At the spine switch level, almost all AI workloads are elephant flows. Spine OCS is nearly free compared to a spine EPS, so free in fact that it lowers the spine capex by 30% and power consumption by 40%.

The thesis is simple: current spine OCS penetration outside of Google is under 5%. That number is gonna increase. Each EPS that gets replaced with an OCS adds to the yearly CAGR. This is an adoption rate story.

However, we still have to get around this insertion loss issue. The current link budget of 4 dB can barely take one OCS hop.

So what’s actually going to spark the adoption?

Coherent-Lite Transceivers!

Optical communication is simply transmitting data through light. There are two ways to encode data in light (known as modulation): IMDD and coherent (no not the company).

IMDD is basically flashing a flashlight on and off. Only encoding signals in brightness.

Coherent modulation is like having one of these:

It encodes signals in brightness, phase, and amplitude.

The benefit of coherent modulation is that it makes it much easier for the receiver to detect the signal, therefore allowing the it to survive a greater insertion loss (higher link budget). This is why coherent is used for long-reach telecom and scale across.

On the other hand, it is much more expensive and complicated, as you can imagine.

Therefore, scale-out is moving to adopt a light version of Coherent known as Coherent-Lite (Yes i know it sounds like a Coherent and Lumentum merger. Who named these modulation schemes?).

As these transceivers get adopted, the link budget doubles or triples, allowing for plenty of room for OCS hops. In fact, we will have so much link room that the light can handle two hops at once. Meaning it’s possible to build networks with a spine and super spine architecture, both of which are OCS.

Google TPU Superpod OCS

Google’s architecture is weird.

Nvidia (NVL72) is very simple and intuitive and easy to understand. Each rack of 72 GPUs is its own scale-up domain (one compute and memory “unit”). The scale-out fabric connects these racks together via transceivers, leaf switches, and spine switches.

Google’s interchip interconnect (ICI) is its scale-up network, but unlike NVL72, it isn’t one rack. Instead, it is a hodgepodge of 9,216 TPUs which share one gigantic memory domain but are connected with “racks” that are each a 4x4x4 cube of 64 TPUs (copper inside the cube, transceivers connecting cubes to each other). That’s why it’s called a superpod.

The pod is shaped like a 3D torus, so basically a giant chip donut.

Each one of these super pods has 48 OCS. Therefore, there is a deterministic port-to-TPU ratio of 1.5:1. So in essence, OCS scales with TPU shipments.

But it gets better. There’s an attach rate story too.

This is based on the excellent work by FundaAI.

FUNDA

Deep|AI Infra 2026: Shifting from "Brain Power" Competition to "Whole-Body" Evolution

In 2026, the focus of AI development has pivoted from chasing high benchmark scores to pursuing AI Agents capable of multi-step reasoning and autonomous action. This infrastructure arms race is undergoing a transformation akin to biological evolution. If an AI system is viewed as an evolving organism: the GPU/TPU represents the calculating brain; Memory and Storage serve as the memory carriers for experience and context; the CPU acts as the hands coordinating tasks; while Optics and Networking function as the limbs supporting systemic data flow and response sensitivity. Under the framework of the Agent Scaling Law, the core bottleneck is no longer just the FLOPS of a single chip (brain power), but rather the communication efficiency (limbs), the memory wall (memory), and the Total Cost of Ownership (TCO…

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5 months ago · 74 likes · FUNDA

A 3D torus is built for an all-reduced communication pattern, which is common in training. Each chip mostly talks to its nearest neighbors, and results ripple through the network like a class of middle schoolers passing notes to each other until everyone reads it.

However, in inference for mixture-of-experts (MoE) models, the communication pattern changes to all-to-all. Every token gets dispatched to separate experts living on chips scattered anywhere in the pod.

Instead of middle schoolers passing notes to each other, it’s like every kid has to talk to every other kid at the same time. But for our purposes, let’s now use a better analogy. Think of the data center doing an all-to-all communication like a city. Every household drives to the far side of the city at once.

Now let’s try to make the problem clear. Imagine in this city there is a central intersection. When there are thousands of cars trying to cross to the other side, there may or may not be mild traffic.

In the data center, this is known as the bisection bandwidth, which becomes a critical spec when all-to-all communication is necessary.

Eventually, this problem needs to be fixed. You’ve thought of every possible solution, but nothing seems to get over the fact that in a two-dimensional plane, there’s only so much space for roads, and you just can’t fit all the cars.

So you hire a genius city planner. By virtue of having infinite tax revenue, this person decides to give everyone a helicopter. Now, there’s not a central intersection. Instead, there’s a central airspace, but because you’ve added a dimension, the bisection bandwidth is no longer a constraint at all.

Bisection bandwidth for N chips given n dimensions scales with the following equation:

bisection bandwidth ∝ N^(n−1)/n

so

N^2/3 in 3D → N^5/6 in 6D → N¹ as n→∞

This is essentially what Google is thinking of doing: moving from a 3D torus to 4D or higher. And each time you increase the dimensionality, the OCS ports per TPU mathematically increase.

This will take a while. It’s not like it’s going to happen in 2027. The patents for a 4D torus are filed, but in TPU v8, Google is sticking with a 3D torus. This is likely something on the same timeline as scale-up TPU, like 2029 to 2030 or later. But it has the potential to double the attach rate in the medium term (3:1 in a 4D torus) and in the very long term, a ceiling of 5x or more (to 10:1 ratio).

Scale-Up OCS

Optical scale-up, the act of connecting the GPUs inside of a rack with fiber instead of copper, is the crown jewel of the CPO market, but for OCS, it is only an interesting call option.

This is because, unlike CPO, scale-up OCS is completely optional!

The idea is to place OCS directly into a rack to replace NVlink switches, but the thing is there’s no law of physics forcing the regular switches to fail in the optical scale-up world. It’s merely a choice by the vendor for what kind of switch they want to use. This is why I won’t be focusing on this market or modeling it very intently.

Types of OCS

As we discussed, the two main drawbacks of optical mirror boxes are the speed of redirecting connections and the insertion loss. These two drawbacks also serve as the main trade-offs between the different types of OCS. We will discuss liquid-crystal and MEMS in this section because they are the two relevant types of OCS for today’s data center deployments. Piezoelectric and Sipho will be saved for later — you will see why.

The simplest way to think about the difference between MEMS and liquid-crystal is that for MEMS you reflect light off of stuff (mirror), and for liquid-crystal you steer light through stuff (medium). All of the spec differences stem from this.

Here is a tier list of the relevant mirror box specs.

Let’s start with insertion loss and cost.

Liquid-crystal and MEMS are very similar cost-wise, but MEMS decisively wins in insertion loss. This is probably the biggest and most important difference between the two types of OCS. MEMS has a 1.5 dB insertion loss versus 3 dB for LC. Decibels are measured on a logarithmic scale too, with 10 dB being one order of magnitude, so 3 dB means that you lose half your signal in one hop. It’s pretty bad.

From Lumentum’s OCS webinar in 2025:

This capability is embodied in the R300, which currently supports up to 300x300 ports with a typical insertion loss of 1.5 dB or less. And a note about the importance of low-loss performance –this is a critical feature, as it is one of the key technical hurdles to the introduction of OCS technology into hyperscale environments. This is seen in the requirement to support additional OCS loss within transceiver link budgets – around 4dB for FR4/DR4 and 6dB for LR4/ER4.

The core mechanism behind this difference is that, for a liquid crystal, you must first split the light, then have it pass through an active medium where some light is absorbed, and then recombine it. Both the splitting and the passing-through-a-medium create insertion loss.

Meanwhile, MEMS is literally a mirror. A literal mirror.

Liquid crystal makes big claims about their reliability versus MEMS, some of which I think are a bit overstated. For example, there is one claim that MEMS wears out after three years because of its moving parts. This fundamentally overlooks the fact that even though the parts move, they don’t slide against each other, and there is, in fact, no friction. Moving parts doesn’t mean sliding parts that wear out.

Google’s MEMS fleet has been in production for a decade with tens of thousands of units. If MEMS switches failed after three years, they would probably notice and say something about it.

However, the reliability of liquid crystal is still much better.

This is due to the system having no moving parts (mirrors) and operating with much lower voltage components.

Now let’s discuss redirection time. This is what dictates how long it takes for the switch to change your port connections.

Currently, MEMS and liquid crystal are about tied at a range of 10-100 ms (liquid crystal slightly slower actually).

However, a new type of liquid crystal in development, ferroelectric LC, switches in 10-100 microseconds instead. This is a a next-generation material for Coherent. As a result, switching time is decisively won by liquid crystal.

But there’s a reason why I put redirection time in C tier.

If you even decide to use OCS, you only have to change port connections when you reconfigure your network. This happens on an order of minutes to days. Microseconds or milliseconds simply do not matter.

Finally, let’s discuss install base.

MEMS wins here for a very simple reason: Google.

Google is by far the largest employer of OCS in the world and has had a fleet of them operating for a decade. They are actually the pioneers of their technology, producing most of their switches in-house (under Palomar brand) before the massive wave of AI demand forced them to externalize. And it’s all MEMS.

Read their Mission Apollo paper if you’re interested in learning about their deployments. But notice how MEMS-centric it is.

This is S tier. This matters a lot. Proven reliability at scale is a defining requirement for data center procurement officers.

Overall, MEMS is way better.

But this doesn’t mean that liquid crystal won’t get any adoption. It is still viable technology and the specs here don’t decide adoption as a binary. If MEMS vendors’ capacity is sold out, hyperscalers will happily buy liquid crystal. Having an OCS at all is what matters more.

Below, I will share my detailed model for the OCS market with accelerator shipments, TPU shipments, external merchant share, ASP, and port ratios informed by industry checks. I will discuss Lumentum and Coherent as players in this market and how I expect it to be split between the two of them, with models for each. Finally, I will share a hidden small-cap OCS vendor.

OCS Market Model

Here is what our discussion about each of the OCS end markets looks like when turned into a model:

Bucket 2 and bucket 3 in reality are the same because they are both spine switches. I just separated out Google from non-Google.

Google has an internal OCS unit called Palomar. It makes up the majority of Google’s OCS consumption today. However, the demand for OCS within Google is growing so fast that its internal supply cannot keep up, and the difference must be filled by merchant capacity.

Based on industry checks, I expect external share to be roughly 50% of Google’s Superpod OCS demand in equilibrium, increasing from 35% today. Google’s spine switch OCS are much more internally supplied, so I model the external merchant share to be much lower.

Unlike Google, the other hyperscalers generally do not have their own internal OCS unit so merchant share is forecasted to be 90%.

This is an elegant market. It’s an almost 50/50 split between Google superpod and spine replacement.

Lumentum

I expect Lumentum to capture a higher share of the overall OCS market due to the superior architecture of MEMS, their incumbency at Google, and their higher revenue run rate today.

Lumentum makes modeling easy for us.

OCS ramps quite a bit faster than lasers because it is mostly assembly and doesn’t need the clean rooms and fab tools that create the crazy lead times.

As I discussed above, I expect MEMS to retain a higher share, and Lumentum, as currently the only supplier of MEMS, is bound to capture most of it.

I forecast their revenue well surpassing their $1 billion 2027 target and reaching over $2 billion by 2028 and $5 billion by 2030, culminating in a high double-digit CAGR.

Coherent

I expect Coherent to be the most viable OCS second source. Both Lumentum and Coherent’s market share, however, will decline as new entrants such as Chinese competitors and ODMs like Molex enter the market due to the relatively lower moat of OCS manufacturing. New entrants will qualify eventually, as OCS doesn’t have the same moat that laser manufacturing does, but I expect this to be limited as there is a lack of scaled players besides Lumentum and Coherent.

Coherent OCS revenue generally hovers around 50-60% of Lumentum’s but is still a substantial contributor to Coherent’s total revenue base.

Hidden Small-Cap OCS Vendor

In Switzerland, there is a tiny company that makes OCS called Huber+Suhner. The ticker is HUBN.

They make the piezoelectric OCS.

Unlike MEMS OCS, which uses micromirrors to redirect light by physically bouncing beams from one fiber to another, piezoelectric OCS uses piezoelectric actuators (tiny structures that move or bend when voltage is applied) to slightly shift optical paths or coupling points (the places where light transfers from one path into another), steering the connection without relying on tilting mirror arrays.

Their revenue is approximately one order of magnitude smaller than Lumentum’s. (CHF is approximately 1 USD, so basically you can treat them like the same.)

Their current run rate is $50 million vs Lumentum’s $400 million, and in 2028 they are projected to make $200 million vs $1.5-2 billion for Lumentum.

But so is their market cap. Even more so, as it is 20x smaller. So technically they have 2x the OCS exposure per $ of market cap that Lumentum does.

So the bet is really on which technology has the better chance to bring forth upside surprise. That means we have to think about the engineering tradeoffs.

Piezoelectric OCS has <1.0 dB insertion loss but is 3x more expensive.

!!!

Is this worth it? I don’t think so.

Insertion loss most likely has diminishing marginal utility. 1.5 dB is enough for one hop using IMDD transceivers and two or more (basically freed up) using coherent-lite. Reducing insertion loss further to <1.0 dB is good, but not the same level of goodness as going from 3.0 dB to 1.5 dB. There are probably very few scenarios in which you would need three or more OCS hops (super-super-spine layer?).

However, I still think this company can be a compelling bet because of what Lumentum said on their last earnings call (which caused a ~15% surge in HUBN).

"In OCS, the multiyear, multibillion-dollar purchase agreement we recently announced ensures sustained long-term growth. Our OCS ramp is largely on track, although our pace and slope are gated by the supply chain. We are experiencing considerable tightness in this product area due largely to the significant step-up in requested output. On the other hand, the number of new opportunities we are seeing for optical switches is putting tension on our road map, and we are having to make choices across the company in order to service them."

If you need OCS and Lumentum can’t provide it, where do you go?

Huber+Suhner is a bet on both OCS overflow demand and piezoelectric cost curve scaling.

By the way, their multiples aren’t all that bad. (this is on SELL-SIDE estimates so real #s prob higher)

Final Thoughts: Better Than CPO?

OCS is a fantastic market, but definitely not better than CPO.

CPO is, in my opinion, the best market in optical and could potentially be the best market in all of AI infra. The attach rate has nearly two orders of magnitude of runway (phase 0 → phase 2) while stacking with the fact that ASPs for UHP lasers are an order of magnitude higher.

With OCS, the two revenue buckets each has only one scaling vector. Spine replacement scales with adoption rate, and Google OCS superpod scales with attach rate. Neither gets the benefit of stacking scaling vectors like CPO does, and the attach rate runway is less than CPO too, at under one order of magnitude.

But the title is a little bit misleading. “Better Than CPO” is a very, very high bar. In terms of being attractive as an overall market, OCS absolutely clears it, and it shall create sustained high double-digit to triple-digit growth until the end of this decade.

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In terms of the YTD the reason why my monthly and weekly portfolio reviews have sort of different numbers is only because of the measurement technique since I’ve been adding capital throughout the year.

(imagine you are adding capital every day to an index fund, and the index is going up, your returns on your brokerage, AKA a MoM or MOIC, would be lower than the returns of the index, AKA capital agnostic CAGR.)

Measuring it the other way would be 195%.

I honestly don’t know which is the better measure, as both are gameable, so whatever. I am up anywhere from 150-200% in less than 1/2 a year without leverage which is not bad in terms of stock picking abilities.

There is a lot of change this time. Specifically, there are 4 new positions a bunch of exits and I’ve made one company ~25% of my portfolio. Also featuring CPO discussion, a cool podcast, sell-side research, macroeconomic theory (not microeconomics this time), and the interesting stuff that happens when you try to DCF a co-location provider.

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

Lumentum (LITE)

Portfolio Allocation: 24.3%

May Performance: -5.25%

Change: Massively added

Yeah, I have a fat retarded LITE position.

Jason's Chips

Optical Illusion: CPO is Dead, Long Live NPO

We have gotten a hilarious amount of discussion in a three-day span about CPO…

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3 months ago · 23 likes · 2 comments · Jason's Chips

CPO is already doing $200-400 million of revenue run rate at this very instance. This is while we are at the very bottom of the CPO S curve. The very first low-yield shipments of scale-out CPO switches (that people seem to be hating on) will S-curve, creating a ton of laser demand. Then phase one scale-up CPO will S-curve starting 2028. Then phase two scale-up CPO will S-curve starting 2030. So it’s just S curve after S curve after S curve.

We also have NPO and Lumentum CEO saying that it could be a larger opportunity than CPO. Obviously, it wouldn’t be the case long-term, but I think he’s referring to the medium-term, especially 2027. NPO seems to be replacing Kyber Racks in Rubin Ultra, which is exciting. They can sell lasers into this market. To anybody who thinks that NPO cannibalizes CPO and is bad for LITE, you can sell me your shares.

I’m also doing more work on OCS, which now seems to be much more compelling than I originally thought.

Bloom Energy (BE)

Portfolio Allocation: 16.4%

May Performance: +0.58%

Change: Massively added

Bloomentum now makes up 40% of my portfolio.

Jason's Chips

Bloom Energy Thesis (Free)

As a Substacker, I am obligated to say that I am releasing this for free to provide an example of what kind of research you would receive with a paid subscription…

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5 months ago · 95 likes · 21 comments · Jason's Chips

I don’t cover this company in as much depth as the Optics names, so we’ll probably have some more articles out on this one. The next two will be on their native 800 VDC advantage and their unit economics, respectively.

There’s this great podcast by K.R. Sridhar (Bloom CEO) that I really like.

This dude is based. You need to listen to him talk on earnings calls and podcasts and whatnot. He will hype you up.

They’ve been doing this stuff since before 2000 and have accumulated hundreds of patents over the years, making tiny little tweaks in the process technology of making fuel cells. Each patent solves a small issue which becomes an integral part without which the whole system cannot function. You think pre-volume upstarts like Ceres can replicate all of that?

SK Hynix (HY9H.F)

Portfolio Allocation: 15.3%

May Performance: +74.34%

Change: Trimmed a tiny bit?

Jason's Chips

Why This Chip Company Is My Biggest Position

Today, I talk about the company that is my biggest position, and it is actually one that I haven’t discussed at all on my Substack…

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4 months ago · 36 likes · 5 comments · Jason's Chips

Not my biggest position anymore.

Memory is still the single biggest binding constraint in AI. Intel (and maybe Samsung) might just solve leading edge logic. InP/CPO won’t be a problem until much later. Everything else only affects a certain architecture (like M9 CCL for Kyber) so in any case, the industry can probably route around it.

Memory is literally a tax on everything and everyone. I think it’s foolish not to have a memory allocation in an AI infrastructure portfolio, and honestly it is more of a hedge.

SK Hynix is also a backdoor Kioxia play. Did you know they own 33% of Kioxia? That is now 9% of their entire market cap because Kioxia has 7x’ed year to date.

Aixtron (AIXA.DE)

Portfolio Allocation: 13.8%

May Performance: +23.97%

My whole portfolio is literally just four companies.

Jason's Chips

Aixtron Q1 2026 Earnings Review | Opto Revised Up Yet Again

This is why you never sell a well-positioned company based on multiples alone…

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5 months ago · 28 likes · 3 comments · Jason's Chips

I pretty much haven’t touched a single share of this company since I bought it in October of last year. LMAO. And I will not ever touch it.

I will be working on finding out what is the purpose of those 80-100 tools, and when that capacity is coming online.

This is important because if they are for CPO (or coming online in 2028 or later which means they are for CPO) then Aixtron’s revenue will inflect as CPO adoption S-curves into 2030.

If they are not for CPO…

Well, remember that the die sizes for CPO are way larger, which requires more MOCVD machine time?

Then those tools are currently for EML/CW, and we would actually need an order of magnitude more tools when CPO and Aixtron become the single biggest binding constraint in all of photonics!

Also, Coherent-Lite could be interesting. Very big surface area.

Also, power semi (GaN and SiC) could be interesting.

Intel (INTC)

Portfolio Allocation: 5.2%

May Performance: +21.38%

Jason's Chips

Intel's Jouney to a Trillion Dollar Company (Q1 2026 Earnings Review)

Let’s talk headline first! I am writing this pre-call so raw dogging it…

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5 months ago · 31 likes · 2 comments · Jason's Chips

I trimmed this one. Nothing really changed except for the valuation. I still think it can go to over $1T, possibly even 2 or 3 trillion, but 1 trillion is less than a double from here.

Unlike with Soitec, I am never gonna sell this thing. We’ll just let this run no matter how expensive it gets.

Degen SPY Calls

Portfolio Allocation: 5.0%

May Performance: +5.26%

Change: Trimmed

I am a little afraid of the macroeconomic theory of higher productivity increasing equilibrium real interest rate (r*) and want to get into robotics, so low key this position will not last.

Basically, here’s the intuition. If AI/Semis/Robotics becomes the industry producing the highest, most unimaginable productivity gains in the economy, it becomes a capital black hole, sucking out investment from other industries. All of a sudden, owning Walmart and Costco at 50x PE or Coca-Cola at 25x starts to make no sense.

But more importantly, nobody would want to put their savings into treasuries and other passive instruments and make a 5% yield when the AI economy is going bananas. Therefore, yields rise, the risk-free rate rises, and macro valuations should compress.

There’s also another lens, which is more academic, which is that demand and supply for savings and investment gets impacted as the demand (investment) has a positive shock (companies building data centers) and the supply (savings) has a negative shock (people taking out their savings to either spend or invest in AI companies).

CoreWeave (CRWV)

Portfolio Allocation: 4.7%

May Performance: -1.85%

I’ll have another article out about CoreWeave shortly. Still think it is a shitco that may eventually un-shit itself.

Think about it this way: currently, CoreWeave signs deals at $9 million per megawatt, while SpaceX just signed $50m/MW with Anthropic and Google. CoreWeave’s margins are absolute dogshit, so they trade at very low multiples. What’s the core difference between CoreWeave’s data centers and Elon’s? What happens to CoreWeave’s dogshit financials and multiples if the revenue per megawatt closes the gap with SpaceX even slightly?

There can be a few mechanisms for this. Here’s one as a teaser: every year, Nvidia passes more value to its customers in performance gains than it is able to capture through higher ASP, and that is structural, because otherwise Nvidia would literally hike its prices by 100x every year. However, the economic value of this performance doesn’t just disappear. If you are the first entity in the chain to have access to this free producer surplus, why wouldn’t you capture it?

SoftBank Group (SFTBY)

Portfolio Allocation: 4.5%

May Performance: +39.12%

Wolfspeed (WOLF) *NEW

Portfolio Allocation: 3.6%

Wolf speed is a book value + long-term technology S-curve dumbbell hybrid and funny shitco memeco play.

The book value is that they have sunk $6 to $7 billion into SiC capacity pre-bankruptcy and now trade at less than half of that.

The long-term technology S-curve is solid-state transformers, which are necessary for the final stage of native 800 VDC, sort of like the scale-up CPO of the power world, which will inflect in 29/30.

Samsung Electronics (005930.KS) *NEW

Portfolio Allocation: 2.8%

Moar memory exposure.

With a bonus of a heavily discounted logic fab, which is implied to be worth 200 billion but probably should be worth way more. This probably doesn’t matter, because even if the value of the logic fab goes ballistic, most of the enterprise value is still memory. It’s really still a memory play. Oh well.

Degen Nvidia Calls *NEW

Portfolio Allocation: 2.4%

Rigaku Holdings (268A.T) *NEW

Portfolio Allocation: 2.0%

Opposite of a shitco.

These guys are a Japanese company that makes X-ray inspection equipment. Onto and Camtek competitor (but it’s better because Onto and Camtek use optical/infrared not X-ray).

Basic thesis is that x-ray machines are great for 3D chip structures and are needed in GAA/CFET, hybrid bonding, GaN/SiC and more. Consensus doesn’t have this thing growing fast at all. I haven’t done too much work into it yet, but it seems like a very safe bet.

More intuitively, you can think about it like: the installed base of X-ray equipment we need for advanced silicon with weird 3D structures is probably a lot higher than what is being implied in Rigaku’s earnings which are projected to grow at low double digits.

Core Scientific (CORZ) *EXIT

I exited to finance my LITE.

I spent more time modeling this one and just concluded it is too hard to have a view on the valuation of these things, because pretty simply, colo providers have to spend double-digit millions per megawatt to make single-digit millions per megawatt per year in revenue. Almost all of it must be equity financed.

So essentially, if you buy the stock today, you really don’t own any assets. It’s just a wrapper on a financing vehicle. Therefore…

Small tweaks in assumptions in CapEx costs, or contractual revenue, or growth rates, or interest rates can move the DCF NPV from negative to like $100b+.

I am still positively biased towards these companies because of their inherent time to power and permitting advantages, but again, it is too hard for me to have a view on the valuation/financials.

But usually whenever I sell something it’s a massive buy signal so this is your chance to buy these guys before a massive deal is announced!

SK Telecom (SKM) *EXIT

Just buy them at IPO honestly. The signal-to-noise ratio here is terrible, and the hedge is just nowhere near good enough lmao.

The takeaway from all of this news aggregated together is actually massively bullish and incremental positive to optics. NOT negative!! I’ll explain why.

All it takes is some very simple logical deduction.

Contents

1. SemiAnalysis Note

2. FundaAI Note

3. What Is NPO and Why NPO

4. Does NPO Use InP & ELS

5. Lumentum at Mizuho

6. Conclusion

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

SemiAnalysis Note

The (very sad) title of their report was “Powered Down, Lights Off.”

I will skip all of the 800 VDC stuff.

For optics, the gist is that they revised down both scale out and scale up CPO in the near term, pushing out adoption.

For scale out, the downward revision is for Spectrum X specifically, and the reasoning is that the optical engine attach yields are bad. Apparently, optical engine attach yields are 95% today (because there are 32 OEs per Spectrum 6 switch). The entire system has a 19% yield. Therefore, because COUPE is incompetent, these switches are being pushed out two quarters. These are the main scale-out CPO deployments, since Ethernet is shipping in higher volume than InfiniBand, which is why the market got so scared.

For scale-up, SemiAnalysis didn’t provide too much new information, but just reiterated that the deployments won’t come until Feynman and won’t ship in high volume until late 2028 or 2029.

But I’ve been saying this too!

I don’t know who thought scale-up CPO would be ramping in 2027. Just because Jensen announced NVL576 for Rubin Ultra doesn’t mean it would actually ship in volume, and it’s not.

Feynman brings the light.

FundaAI Note

At the very same time, FundaAI published a note claiming that NPO deployments are going to double.

I think the reason has to do with Kyber being scrapped.

Kyber racks require high-grade (M9) CCL (copper-clad laminate) because the per-lane rates are increasing, the layer counts per tray are increasing, and the cableless design pushes these signals through the midplanes and orthogonal backplanes, putting even more pressure on the CCL for M9 CCL. Traditional glass fiber won’t cut it. You need quartz fiber, which is much harder to manufacture and whose supply chain is much less mature.

This supply chain probably isn’t ready.

Therefore, whatever shipments were relegated to Kyber for Rubin Ultra probably switched over to NPO.

Now notice: Mass adoption of NPO plus rumors of CPO delay sounds like NPO is replacing CPO, but actually that’s not what happened at all. CPO was always going to be 28/29, and NPO is actually replacing Kyber, meaning that we have more incremental optical content than before.

The complete opposite of the consensus perception of this “optical illusion”. (get it)

What Is NPO and Why NPO

NPO is Near Packaged Optics. This is like co-packaged optics, except the optics aren’t co-packaged with the XPU. It’s only packaged near the XPU. Easy enough.

As a result, you would avoid this compounding yield problem that SemiAnalysis claims killed CPO. NPO is socketable. It is much, much easier.

Does NPO Use InP & ELS

Probably.

And this is what makes the market reaction to all of this so silly.

Look at the diagram for NPO.

According to this design (SemiAnalysis), the only difference is in the packaging. The laser, the fiber, and the optical engine have the exact same content. This means that every single NPO lane is just as much InP revenue for Lumentum and others as CPO.

Now I must caveat this with the fact that this design (specifically using an external laser source) is not forced for NPO the same way it is for CPO. This is because external lasers are the solution to heat (lasers hate being near the hot XPU (serviceability) and laser failing can just be swapped if it’s external instead of blowing up the entire tray; but for NPO, the module itself is placed away from the XPU and is also socketed, which reduces blast radius.

It seems like if NPO uses InP, the design is still external lasers. If NPO uses VCSEL, the lasers are likely internalized. However, because we’re talking about 1.6T and 3.2T, if a slow and wide approach is not adopted, lane rates are 200G or higher, which is beyond what VCSELs can support. Therefore, it is most likely that NPO uses the same ELS architecture that CPO does. It is okay if this architecture is not permanent, because in a few years CPO will be here and force external lasers to stay anyways.

Lumentum at Mizuho

There are two important takeaways from their comments at this conference (which occurred at the same time as the SemiAnalysis note).

First is their stance towards NPO.

Yeah, that’s right. Lumentum thinks NPO could be an even bigger opportunity than CPO (in the medium term).

This is only possible if NPO uses the same ELS architecture as CPO. As selling commodity lasers into the NPO market would simply never have numbers that can eclipse anything involving UHP CPO lasers (which are ~10x the price) no matter how many optical engines there are.

The second is that Michael Hurlston confirmed scale-out CPO could contribute $50 to $100 million of incremental revenue THIS QUARTER.

That is a $200-$400m run rate in the middle of 2026, which likely implies $400m full year revenue, which is 50-100k switches according to my flawless model.

SemiAnalysis says, “The street currently models 60 to 100k scale-out CPO switches shipped by 2027... We think today’s pace of scale-out production is too low to reach this bogey.”

According to Lumentum’s actual revenue, it seems like today’s pace of scale-out production is not too low to reach this bogey.

Conclusion

Based on the evidence I see in the past few days, the optical story has gotten better, not worse.

Scale-out CPO seem to be on track and pushing Lumentum’s revenue this quarter to the high end of their guidance.

Scale up CPO was never delayed, as it was always shipping with Feynman, not Rubin Ultra, in the first place.

And NPO does not cannibalize CPO. Instead, it cannibalizes the Kyber racks, making it purely incremental content for optics.

If NPO uses ELS, NPO would contribute the exact same revenue to optical players as CPO, which, based on Lumentum’s comments about the NPO market, seems by far the most likely scenario.

This is the view from the top of the Taipei 101. It’s really a beautiful city.

Anyways Computex basically takes place inside of this building and there’s a whole bunch of booths and it is an absolute meat fest (very packed).

There was a ton of alpha to be found by looking at the racks and talking to the various interesting people at the booths.

We will first highlight various interesting exhibits from investors POV. We will then talk about CPO. The main takeaway I’ve had is the end-state of scale-up CPO (and it is incredibly important!)

Contents

1. Immersion Cooling

2. Fuel Cells

3. Hiwin (Robotics Supplier)

4. DRAM

5. Kyber Racks

6. Astera Labs

7. Nvidia RTX Spark (Laptops)

8. MediaTek MicroLED

9. Scale-Out CPO

10. Scale-Up CPO, Takeaways for Stonks, and Lumentum EPS

SemiAnalysis Giveaway: The first person to subscribe using the paywall on this post will be selected to receive one free month of SemiAnalysis (sent to your email).

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

Immersion Cooling

There is this company called QuettaFlow that literally submerges GPUs in liquid to cool them.

Isn’t that so sick?

Unfortunately, you can’t put an NVL72 rack in this liquid, as you may imagine. This is only for small chunks of compute, so basically enterprise on-prem.

The liquid isn’t water (duh). It is a non-conductive fluid that is a by-product of oil. You can plug stuff into the rack while it’s submerged. I actually touched it. It is very oily and greasy.

The benefits are that it is much cheaper (40-50%), much more compact (no IT room or raised floor), and saves a ton of electricity.

They’re private, of course, but fascinated to see where this tech can go.

Fuel Cells

Funny story.

We were at the Vertiv booth and asked the guy there about this 800VDC power module and what it does.

It is a combined transformer and rectifier that turns AC medium voltage from the grid into 800 VDC.

This is very big and expensive. I think they said like $3M ASP.

So we asked the guy, “What if you just had 800 VDC natively? Then you wouldn’t need this box, right?”

He said “Well, where would you get that?”

LOL

Jason's Chips

Bloom Energy Thesis (Free)

As a Substacker, I am obligated to say that I am releasing this for free to provide an example of what kind of research you would receive with a paid subscription…

Read more

5 months ago · 92 likes · 20 comments · Jason's Chips

Then we visited a booth for a company called Delta Electronics. They are competitor to Vertiv and Schneider. Basically, liquid cooling and stuff.

But did you know that they also have an SOFC solution?

Unlike Bloom, which uses ceramic plates, Delta licenses Ceres’ IP, which actually uses steel. Obviously specs are inferior to Bloom currently, so it’s more of an overflow capacity play.

They are currently shipping small volumes (30 to 50 MW) and installing them in Taiwan. They’re not fully independently scaled commercially, also, as the purpose of these fuel cells is more to provide a full portfolio of power solutions complementing their Vertiv-like products.

Ticker is 2308 on the Taiwan exchange.

Hiwin (Robotics Supplier)

Hiwin is a Taiwanese screw maker that supplies into robotics. They make actuators (components that help robots move). Did you know that actuators actually make up most of a robot’s BOM?

Interestingly, most of their sales are actually to North America, to companies like Tesla. This is important because a lot of this stuff comes from China, so American companies would find suppliers like this very attractive as a geopolitically safe option.

In the middle is their best component, which is a linear actuator. They are better (higher ASP, less commoditized) than the rotary ones on the sides.

I looked into them a bit further. Turns out that 50% of their sales are actually to the semis market. So yeah, here’s a company that has exposure to both robotics and semis. If you are interested, the ticker is 2049 on the Taiwan exchange. However, as you might imagine, screws are quite commoditized. They only have about 10% market share. LOL. And they trade at 40x multiple on sell-side estimates. I honestly would have expected a way lower multiple for a business like this.

DRAM

How to invest in semis 101:

1. Look at the PCB.

2. Identify what has the most surface area.

3. Buy.

One recurring theme that I noticed is how literally every single tray that you see at Computex has a shit ton of DRAM. It sounds obvious, but you really need to see it for yourself to intuitively grasp how much DRAM is in everything.

For example, this is the Vera CPU compute tray.

Those SOCAMM modules are stacked too, so it’s actually even more surface area than it appears to be.

Being bullish on CPU proliferation for agents is almost just as much bullish on DRAM. As it would drastically increase the total base of compute (accelerated or not) to which memory is attached.

Kyber Racks

Kyber racks are so cool.

GPUs go in vertically from the front. NVSwitch modules go in horizontally from the back. They meet in the middle via orthogonal midplane. Super compact! Save space!

This means you can fit 144 GPUs in one rack. It’s very beautiful and elegant. There are no cables, either.

However, the volumes at which they can actually be shipped for Rubin Ultra are constrained by the supply chain. Kyber racks require high-grade (M9) CCL (copper-clad laminate), because the per-lane rates are increasing, the layer counts per tray are increasing, and the cableless design pushes these signals through the midplanes and orthogonal backplanes, putting even more pressure on the CCL for M9 CCL. Traditional glass fiber won’t cut it. You need quartz fiber, which is much harder to manufacture and whose supply chain is much less mature.

If it does ramp, this has significant implications for future data center design. If data centers become much more compact, 800 VDC might be able to span the whole shell without needing to go through lossy transformer and rectifier steps (800 VDC cannot travel long distances). This is incredibly bullish for Bloom, as they output 800 VDC natively. Meaning that the TCO of a fuel cell becomes materially more competitive if smaller form factor racks and data centers get wider adoption. This deserves an entire article of its own.

Astera Labs

Asteria Labs makes connectivity chips, like retimers (which are chips that clean up signals and retimes it to the clock) for copper communication (CXL and PCIe).

Astera Labs is a huge Trainium supplier. The 2025 10K says that one customer was 70% of revenues. I wonder who that is!

(This is also why Astera is Gavin Baker’s biggest position. Gavin is a believer that Trainium is an even better ASIC than TPUs.)

Think of Trainium as the Amazon basics of XPUs.

SemiAnalysis

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10 months ago · 144 likes · 3 comments · Dylan Patel, Daniel Nishball, Wega Chu, Myron Xie, Ivan Chiam, Clara Ee, Cheang Kang Wen, Wei Zhou, Jeremie Eliahou Ontiveros, and Tanj Bennett

They are literally air-cooled and also use PCIe for scale-up like regular computers. Sometimes I am flabbergasted that compute which doesn’t use NVLink… works.

But did you know that Astera Labs actually has an LPO solution?

(An LPO is just a transceiver without a DSP. Think of it like the transceiver is to LPOs as an AEC is to passive copper.)

They don’t actually make the LPO module itself. They sell the LPO switch ASIC and the software that modulates the SerDes signal.

This can be used for PCIe scale-up!

An LPO has the same latency as passive copper DACs because there is no retiming. Compare that with an AEC, which has active data processing components. It is pretty much strictly better, as the LPO can reach up to 50m while the DAC fails within a few.

Here is an eye diagram (PAM4, you can tell because there are three eyes).

I have no opinion on this stock besides that it is a good tracker for Trainium capex.

Nvidia RTX Spark (Laptops)

Nvidia’s new agentic laptops. The only thing I have to say here is that isn’t it so weird that they are turned off and facing away from the crowd? I wanted to try them, but they don’t even work. This is just fueling more criticism of their ARM + Windows design.

MediaTek MicroLED

For some reason, MediaTek is obsessed with microLED for scale-up CPO. When I was at their booth, a ton of space was dedicated to this (very widely hated) solution while their custom ASICs weren't present at all.

Interesting.

Micro-LEDs are an alternative to lasers. A lot of photonics engineers don’t like them because laser light is basically very concentrated (coherent, highly directional) and it is also a single wavelength (linewidth anyone?) while LED light is very diffuse.

Like literally think about the LEDs in your house versus a laser that you can shine.

As a result, it is much harder for the receiver to pick up the signal, and thus you have much higher insertion loss and bit error rate. This is a pretty fundamental difference between the two technologies that is sort of glossed over in these booths.

But they do have a lot of claimed advantages. They are much more power efficient, have superior thermal resilience and reliability, and can be integrated directly onto the CMOS transceiver chip.

Micro-LEDs are very short-reach. I was at the Molex booth, which is an ODM for micro-LEDs, and they said that it only reaches up to several meters, meaning that this is a potential scale-up CPO candidate.

Scale-Out CPO

There are two types of scale-out CPO switches: InfiniBand (Quantum-X) and Ethernet (Spectrum-X).

Let’s start with the InfiniBand one.

There are 18 ELS (external laser) modules (down on the bottom of top pic) and 4 switch ASICs with 18 optical engines surrounding each (see below, optical engines circled in red).

Now for Spectrum-X. There are 16 ELS… but only one ASIC!

That one ASIC has 32 optical engines around it. So less than 1/2 optical engines total, and 2:1 OE to ELS ratio rather than 4:1.

The ELS are also liquid-cooled, unlike quantum X where the ELS are air-cooled.

Here is the higher radix one. Basically 4 switches put together.

And the Spectrum-6 rack, which is four high radix switches put together (16 normal switches). This supports eight NVL 72 racks.

Scale-Up CPO, Takeaways for Stonks, Lumentum EPS

Below the paywall, we will discuss how my models (CPO ELS/OE builds) have changed after looking at Nvidia’s reference designs, the crazy mock scale-up CPO rack I saw (and the face-slapping implications for the scale-up CPO endgame I realized), and takeaways for optical stonks.

I will be providing the answer to the question I posed in this tweet.

We will be talking a lot about ratios and numbers and assumptions because small changes to these can either blow out or tank out-year revenues for optical companies.

And I will update my Lumentum model & EPS estimates.

This is my main CPO build. It’s from my Lumentum model, but I borrow this for all of my other CPO companies.

First, let’s update our scale-out CPO assumptions.

If each Spectrum 6 SPX rack has 16 Spectrum-X switches and supports eight NVL72 racks, then the XPUs per leaf switch are 36, which would end up almost doubling the scale-out OCS shipments adopting this. (Note that this is for Nvidia Spectrum-X only. Non-Nvidia and Nvidia Quantum-X are likely to be higher.)

Plus, talking to the guy at the booth made me realize that my adoption percentage assumptions are probably too conservative. He pretty much reinforced that customers liked the CPO solution way more because it has tons of advantages with almost no drawbacks. It’s got higher performance, higher reliability, and a lower price. The power consumption is an entire order of magnitude lower because you are cutting out the lossy copper signal that would require the DSP. My adoption rate was lower just for conservatism and uncertainty purposes, but now it seems like that is kind of unnecessary.

Also, I am changing the ELS per switch in the early years to 16 to reflect majority Ethernet adoption.

With these new assumptions, 2028 scale-out ELS shipments go up almost 3x. This is why the optical world has such high torque. Even minor changes to estimates on adoption scale can completely blow out your numbers.

Now let’s discuss scale-up CPO. This is the crazy rack I was talking about. I want you to examine it for at least 30 seconds. Really let it sink in.

LOOK AT HOW MANY ELS MODULES THERE ARE!!! (The blue pluggable-looking things)

(Take this all with a grain of salt because it is not a reference design.)

This is the final phase of scale of CPO. The phase two that Lumentum discussed at OFC.

There are literally 16 ELS in each and every compute tray. That is as many ELS in a compute tray as there are in a Spectrum X scale-out switch. If each compute tray has two XPUs, the ELS to XPU ratio blows out from approximately 0.5:1 (in scale-out only) to 8:1 (in full scale-up).

You can get to this number theoretically through research, but seeing it in person is a completely different experience. You can literally feel the laser content. Now do optical stocks look overvalued?

In addition, in this concept design there are also 16 optical engines per tray, which means that each ELS drives one optical engine compared to two or more in scale out. I did model the OE to ELS ratio decreasing over time, but this shows us that the industry wants to move to one-to-one much faster than I initially thought (likely due to higher lane speeds). This is very bullish for indium phosphide/lasers and slightly bearish for SiPho and SOI.

Phase 1 scale up CPO, which is to connect adjacent racks with the light source on the switch trays, goes from approximately 2.75 ELS per GPU to 4.0. At 50% adoption and with only Nvidia’s shipments modeled, this is already 1.5x more volume than scale-out CPO at full throttle.

Based on our rack, phase 2 scale-up CPO starts at 8 ELS per GPU and is fully incremental!

The market really never internalized this slide from Lumentum. Lumentum wasn’t lying. Each phase is actually 3-4x more lasers, and the numbers based on this simple truth are terrifying.

Here’s the final model (phase 2 still excluded because too hard to model; too far away). I also increased my laser ASP assumptions to $50 again as a midpoint to the conservative $35 I heard back in February and a more bullish $80 assumption from some conversations that I had at Computex and increased my gross margin assumptions to 75% to be a conservative reflection of industry chatter about 80%+ gross margins for Lumentum’s CPO lasers.

According to this model, they will now do about $5 billion of revenue in 2028, right in line with their $5b Greensboro fab revenue capacity guidance.

They now also trade at under 16x on 2028 EPS, which are projected to reach $57. And on out years, like 2029-2030... let’s not talk about it. (and then after that there’s another order of magnitude step-up with phase two scale-up. LMAO)

BTW, this is also unimaginably bullish for Aixtron and AXTI.

Finally, I want to talk about copper.

There are many racks at Computex. Everyone is usually standing in front of these racks and gawking at the compute trays, but actually, if you walk behind them, you can see something really interesting.

Look at how many copper cables there are! The sheer weight of this copper must be enormous.

Now imagine how much worse it gets when we try to push higher bandwidths, necessitating even wider cables (due to the skin effect). Do you see why we need CPO?

All of this copper is going to disappear in 2030 when we get full optical scale up. Now, this probably isn’t actionable at all anytime soon, but long term you don’t want to be the supplier selling this stuff. This is part of the reason why Credo is pivoting to optics so aggressively with both DSPs and micro LEDs.

Thus, the implications here are that the share price and numbers of copper companies (not soon, but eventually) are going to tank, and that you can predict that everyone will try to squeeze into the optics market in any way they can. The more commoditized parts of optics are about to become REALLY commoditized.

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

I am a wizard and absolutely nailed their earnings with my tweet.

They did, in fact, announce that their "opportunity pipeline" expanded again, while being simultaneously missing on revenues.

Revenue Misses

I will bash them in other areas, but I am actually not going to do so here. I completely buy this excuse, because if this was any other company that I cover, I would have given them the benefit of the doubt as well. This honestly doesn’t matter as much at all for whether or not their CPO shenanigans will take off.

Opportunity Pipeline

Bashing time! If I were sell-side, I would be absolutely dishing out questions to management over this. Every single mechanism for defining the opportunity pipeline is up to the discretion of management. Not a single one is objective. Not a single one relies on contracts.

What does meaningful discussions mean? What does good conviction mean? What does determining that Sivers’s technology is a good fit mean? No one knows. The management can define those however they want. This doesn’t necessarily lead to the opportunity pipeline being an inflated metric per se. Management could be even more conservative if they chose to. It just means that this is a metric that is manipulatable and should mostly be treated as noise and not signal. I’m sure if you had the right incentives, you can easily manipulate this pipeline to be an entire order of magnitude larger or smaller than it currently is.

The biggest red flag is that Vickram Vathulya does not address any forward revenue guidance.

This question is a clear invitation to share numbers, and it was dismissed with a one-sentence answer on their themes.

Their end markets are growing way faster than this BTW. CPO should be triple-digit growth.

No qualifications, no production volume orders, nothing changed.

Competition

Here they just completely conceded that they are worse than Lumentum in every way. All they needed to mention, like most companies when they’re asked this kind of question, was at least one area in which they are competitive and to talk that up as the more important trade-off. You can see Coherent doing this all the time with their 6-inch wafers, even though they are uncompetitive everywhere else, but they still have something to talk about.

The only response Sivers could give was “…but the pie is growing!” TAM doesn’t pay the bills if you can capture none of it.

Margins

This is very good. COHR GMs are barely above 40% for reference. Achieving this would actually be remarkable. Credit where credit is due.

Conclusion

This last question in the Q&A captures perfectly the essence of Sivers today.

Maybe because they’re not actually a volume supplier to the market since they haven’t qualified anywhere?

Everything else is noise until they give purchase order announcements with clear numerical amounts, and provide year-by-year revenue guidance. Until then, they’re a startup, and nothing has changed.

Both on the good side and bad, for example, the revenue miss today doesn’t matter at all, and neither does the “opportunity pipeline.” I guess that just means I’m saying that earnings don’t matter at all. LMAO.

See you next quarter!

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

Contents

1. Headline Numbers and Press Release

2. Memory Downturn

3. Price Action

4. Capex, Working Capital, and Cash Flow

5. Capacity and Contribution Margin

6. Physical AI

7. Photonics

8. Overall Thoughts (and My Positioning)

Headline Numbers and Press Release

First, the press release.

Revenue massively beat, however gross margin massively missed, and so did EBITDA margin, EBIT, and net income. Oh god. However, cash flow generation beat massively. Overall, just very confusing, but it makes a lot more sense once you actually listen to the call.

Big beat in Auto and Industrial??

Price Action

The stock reacted positively, but I am extremely, extremely certain that the price action today is actually quite low signal because a whole bunch of hedgies were short this thing, expecting management to kitchen sink it and absolutely rug pull the guidance due to the whole mobile memory situation.

And then they ended up not rug-pulling it as much as they think, so shorts covering it like crazy. I honestly think it had nothing to do with photonics. Believe it or not. Funny enough. And the stuff they said about photonics is mostly confirmation, clarification, and realization of things that we already know.

This article was actually vindicated down to every last word. Now I can say I told you so.

Memory Downturn

Overall, their starting tone was “patient guys, we are still in recovery mode,” near the beginning. Throughout the length of this two-hour long-ahh call, it slowly turned more positive and more forward-looking.

But surprisingly, I heard very little of memory itself, surprisingly little, which is… good? I mean, I guess people thought the BOM pressure would be a lot worse than it actually was.

Now turning to the outlook. This doesn’t seem too bad. Low key, I don’t really care about mobile, like, at all. But sequential improvements? Proven improvement being less pronounced than previous years isn’t “the market is literally crashing because of memory and we’re going bankrupt.” So I guess the short sellers have nothing to short anymore!

Capex, Working Capital, and Cash Flow

Apparently, the French are very good at working capital management.

If you hated working capital and whatnot from learning accounting, I am with you. I generally don’t really give a shit, since stocks are forward-looking, but in this case they did so much working capital management that they flipped free cash flow insanely positive so we actually need to talk about it.

Working capital is basically all of the capital tied up in temporary, nonpermanent assets like inventory, accounts receivables, etc.

Anyways, the gist of it is that they unloaded their inventories like crazy to clear working capital and generate cash so that they can, you know, invest in stuff.

And then on CapEx, they did a lot of good stuff here too, reducing CapEx overall and then redirecting it towards photonics, which is exactly the right thing to do. Very good job.

Capacity and Contribution Margin

One of the main claims in my original thesis was that their capacity is fungible. That means that their stupid RF overbuild, which they got bitch-slapped by memory for, is now going to be a tailwind, Citrini supply-chain-inheritance style.

And today, we get a whole slide about it, with plans for each fab! That’s pretty neat.

They also clarified their contribution margin economics. Incremental revenue contribution margin is currently 60% because of how underutilized it is, but gets closer to 50% in equilibrium. They specifically said that EUR 100m of revenue contributes EUR 50m of gross margin, which is actually exactly as I modeled. Nothing new there.

Physical AI

One of the most interesting things that I noticed from this call is actually their focus on physical AI. I was expecting photonics to get 100% air time today, but instead photonics got like 60% air time while physical AI got a surprising 40% (not real numbers, of course).

FD-SOI for robotics is actually very interesting because always-on devices or robots need very low power consumption.

And they pitched physical AI as the end state of AI after agentic.

Photonics

Now, on to the meat of this call, photonics. First is that they passed $100M of photonics revenue in FY26, perfectly matching the guidance that they gave in the past.

They did say that demand has reflected sharply since March. Now they have a lot more visibility, and they changed their guide from growing 20 to 30% year over year (which is laughably low) to “something above 30%.” But okay, come on, we obviously know that it’s way above that. It instead should be 50 to 100%, but it will take these conservative French folk a while to update their priors on AI growth.

They talked a lot about their photonics moat today, and, like I said in this piece, I would not fade them on this at all.

Jason's Chips

The Soitec Series | Part 2: Wafer Manufacturing and the Smart Cut Moat

I wish this was a real product…

Read more

6 months ago · 57 likes · 3 comments · Jason's Chips

They have a practical monopoly (~95% share) on photonics SOI, almost as strong as Aixtron’s monopoly on InP MOCVD.

Actively renewing 4,800 patterns with decades of process learning across crystal engineering, interface engineering, refresh and repolish, and advanced processing. Photonics is much harder than regular SOI and requires precision in defects, human formity, and roughness, again just like I said in my article.

They were asked about competition and potential replacements, and their answer was pretty good. They said that there will be competition, but reinforced all of Soitec’s advantages. I am not at all concerned about competition for them.

They were also asked about TFLN and replacement potential for silicon photonics, as silicon photonics does not have the modulation speed required for higher data rates. However, they clarified that InP and TFLN are the same thing, and they have already highlighted InP as one of their key future investment areas. Also, TFLN and silicon photonics are complementary. You can add this material on top of an SOI wafer, so in reality it’s not a concern at all.

In terms of visibility, they said that there is visibility even in the long term, but what they want is for customers to have “skin in the game,” AKA prepayments. I’m not sure why they want prepayments so badly, given that they already have the capacity, but I think that, just like with Aixtron, these Europeans who went through a cyclical downturn are really conservative. I think that’s the reason why their guidance has been so low in the past.

They were also asked a few questions on CPO, which I had high hopes for but really didn’t get much out of it. Mostly clarifying that no, they are separate, that CPO is used for scale up, and they won’t really cannibalize each other, which is stuff that we already know. I was hoping for some clarity on potential mix of CPO once the technology matures so I can get a sense of how strong CPO SOI content is compared to transceivers, but we didn’t get that, unfortunately.

Finally, they had a comment on pricing dynamics, where the profitability of photonics is much better, and it’s very clear that when they shift the mix to photonics, they improve the bottom line. They have a firmer hand in pricing than they did in their other end markets, which is again something we already know, but it’s good that they are reinforcing it.

Overall Thoughts

I have a few thoughts here, but my main conclusion is that this is pretty positive. Not enough to convince me to get back in (yet), but still positive.

I can yap all I want about thesis confirmation, yada yada yada, but that would just be some AI-like slop. I’m just going to say that, to me, what is new here is really hearing management talk in this post-CFO inflection era and getting to know them better. I really like the team. They are very conservative. They’re very prudent, and they seem to be very good at what they do. That, to me, is the biggest incremental new information.

On top of that, robotics may surprise us in the future, but it’s not something that will move their valuation anytime soon. The story is still photonics.

The reason I’m not getting back in is I still don’t have clarity on their unit economics for CPO. This is too expensive to just trade off of transceivers (which is the same for basically every optics name today. You absolutely need CPO).

I am very confident that InP demand will explode with CPO, but less confident about SiPho demand. That’s why I prefer LITE and AIXA (and you could even argue AXTI) because it’s very clear that InP demand is way higher per UHP laser than per EML or low power CW. And this means aggregate InP demand for CPO will be much higher than for pluggables.

But will CPO as a paradigm use SiPho more or less intensely than 1.6T (SiPho-loving generation) transceivers? I don’t know yet.

It was only a few months ago when photonics was a niche, technically complex subsector of a subsector of a subsector of the AI infrastructure trade, covered by small, undiscovered, and specialized analysts. Today, it shares an investor base with 2021 NFTs and 2024 Solana meme coins.

But unlike crypto, the technology and fundamentals are still there!

So it’s truly become a fascinating contradiction where on one side there are companies with real technology and an almost perfect market position. There is some hype around them, but that hype is not nearly enough, and they still present a great opportunity (see ). On the other side there is Sivers.

Sivers is special. Before all the speculation promoted by unethical large social media accounts, there was a legit investment thesis! Credit to the several analysts that found it pre-cult.

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Moody

Sivers Semiconductors: A Swedish Technology Dwarf Punching Far Above Its Weight in Three of Today’s Hottest Tech-Trends

When searching for the next semiconductor highflyer, most investors look to California, Taiwan, or South Korea. The fact that a Swedish company with just 125 employees, headquartered in the Stockholm suburb of Kista, is simultaneously fighting on three of the most exciting technology frontlines of our time – AI data centers, satellite internet, and auto…

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7 months ago · 44 likes · 3 comments · Moody

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Silicon Matter

Sivers Semiconductors: a $130m mcap co-packaged optics, LiDAR and SATCOM play

Intro I’ve been sitting on this piece about Sivers Semiconductors for a while, but ahead of this years’ OFC conference I believe it’s prudent to push the publish button. For those unfamiliar with Sivers, it’s a relatively asset-light and Sweden-based technology company led by CEO Vickram Vathulya, with annual revenues of $33 million and approximately 130…

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6 months ago · 70 likes · Silicon Matter

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Gaetano

$SIVE Deep Dive

Sivers Semiconductors ($SIVE) is one of the more interesting smaller names in this part of the market right now. I have received more requests on $SIVE than any other company in this sector…

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6 months ago · 46 likes · 9 comments · Gaetano

Now I will pretend that Sivers is $130 million market cap again, and pitch the original thesis. It is by doing this that we can fully understand why it has broken after a 20x, unlike names like and .

We will be analyzing Sivers (and finding out why it is insanely overvalued) through a purely fundamental lens. I will not comment on the market structure or price action or ethical/legal concerns, or criticize any of the individuals that have promoted this name. I will instead save that for my tweets (lol).

Oh, by the way, for anybody asking me to short, I wish I could, but I can’t because IBKR won’t let me. My account is restricted to cash only.

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

Contents

1. The Original Thesis

2. The Valuation is Absurd

3. Sivers 101: Opportunity Pipeline & NRE

4. The (Fabricated) Bull Case

5. Why Is Sivers Fabless?

6. There is No Moat

7. The Wrong Architecture

8. Conclusion

The Original Thesis

Sivers is a company with two segments: wireless and photonics.

Wireless makes up 70% of 2025 full-year revenues. Photonics (which includes both data center photonics and LIDAR) makes up the other 30%.

The company is cheap. With a $130 million market cap and around $33 million of revenue, Sivers trades at almost exactly 4x EV/revenue.

Profitability is constrained as EBITDA is currently negative, but that’s the whole point. A company that is cheap on EV/revenue with negative EBITDA that has a hidden gem segment (photonics) can show massive operating leverage if that hidden gem segment explodes.

This is precisely what sell side projects. While the legacy wireless segment is forecasted with pretty unexciting growth (5G and radar and satellite stuff), photonics, which includes both LIDAR needed for physical AI and, most importantly, CPO for data centers, carries the company to double-digit sales CAGR and their 20% EBITDA margin goal.

With revenues doubling by 2028 and EBITDA margin inflecting positive, suddenly you go from 4x EV/revenue to 2x EV/revenue and 10x EV/EBITDA. By 2028, photonics would make up half of the entire company’s sales, making this an attractive bet.

Not much has to go right here. At a market cap of $130 million, the thesis can simply rely on management delivering on their own stated goals.

The Valuation Is Absurd

The sell-side price target is less than 10% of the current market price, which I find absurdly funny. (It is really funny.)

I think the ridiculousness of this valuation is best explained by my tweets during my retard crusade last weekend.

And the way it got to this valuation is also extremely unhealthy.

As you can imagine, if the stock is nearly 20x more expensive at a $2.3 billion valuation, the old thesis doesn’t work anymore.

This is not true for all companies. Some, like or , sell a raw material or commodity whose supply/demand scarcity dynamics have no natural ceiling. This means that one thesis (memory ASP go brr) can justify nearly any valuation.

But for other companies competing in the 10-bagger arena, the thesis must evolve as the valuation gets more stretched.

Sivers could rely on a simple CAGR back at $130 million. At $2.3 billion, they now trade at more than 230x their disclosed 2025 photonics revenue. Keep in mind that the photonic segment isn’t purely data center revenue, either. It also includes LIDAR, and they do not break down sub-segment granularity, so in reality, the actual multiple is higher. I am also only able to use trailing multiples, as the company has not disclosed a single DC photonics volume purchase order or given any DC photonics revenue guidance. They are basically a pre-qualification startup.

All management disclosed is their goal of compounding their revenue at 25 to 30% CAGR, expanding to 65% gross margin, reducing R&D to 20% of revenue, and having an EBITDA margin around 30%.

“Based on the cost structure and margin profile of the business, we would expect to reach cash flow breakeven at annual revenues of approximately $50 million-$55 million, and 65% of revenue stemming from products. This we are targeting in roughly two years’ time. Our long-term ambition is to sustain 25%-30% revenue CAGR, with fabless financial KPIs at around a 65% gross margin, R&D costs of around 20% of revenues, and an EBITDA margin around 30%. We are striving for world-class performance because we believe we have the technology to achieve it.”

This is no longer aggressive enough to save the stock.

Now, we have to evaluate whether there can be an order one or two order of magnitude step function growth from a sudden qualification breakthrough along with massive purchase orders (that can actually be manufactured with their current owned capacity and WIN allocation) that can even remotely justify the current valuation levels. This also means that Lidar and Wireless are pretty much irrelevant because the only segment that could be explosive enough to drive a fundamental breakthrough that justifies the current valuation is the massive CPO market. Other factors that people usually consider “bullish” like Chips Act funding (which is actually for their wireless segment for defense) and a Nasdaq listing (with like $16 million of inflows or something) also, don’t really matter at a $2.5 billion market cap.

If photonics breaks, the entire story breaks too.

Sivers 101: Opportunity Pipeline & NRE

Every earnings call, Sivers presents a KPI known as their Opportunity Pipeline. Their Opportunity Pipeline right now is $453 million, which is up 64% in 2025.

It sounds really big and cool because it takes the place of a number of other companies’ reports, which is very important: the backlog. However, the opportunity pipeline is not a backlog at all, not even close, and treating it as a backlog is extremely misleading.

The Opportunity Pipeline is literally everyone that they’re talking to. If they’re having a conversation, it’s part of their Opportunity Pipeline. For it to actually convert into contracted backlog, they need to move into evaluation and sampling, which is still very far away. Then get a design win and finally make it to production orders. I’ve never seen any other company in the world report the numbers this way. It makes it extremely inflated.

In my estimation, only about 10 to 20% of the Opportunity Pipeline actually converts to backlog. Which is around $68 million of their $453 million opportunity pipeline.

I started from the idea that the $453m opportunity pipeline is a five-year, non-binding funnel, not a one-year order book. If all of that were close to backlog, Sivers would already have several years of contracted revenue sitting behind a company that only did about SEK 306m / ~$30m of revenue in 2025. That does not fit the disclosures: contract liabilities were only SEK 11.6m, management says the pipeline is non-binding, and much of Photonics is still sampling/qualification. So the true committed layer has to be much smaller than the headline pipeline.

Then I sanity-checked it from the other direction: Sivers still needs enough near-term committed or near-committed work to support 2026 revenue around SEK 360-376m, plus named programs like CHIPS, Tachyon, Doosan, ALL.SPACE, LiDAR, and FWA. That gets you to a few hundred million SEK of credible revenue-converting opportunity, but not billions. Converting that into pipeline percentage: 10% of $453m is ~$45m, 15% is ~$68m, and 20% is ~$91m. That range maps to roughly 1.5-3.0x FY2025 revenue, which feels plausible for a mix of signed work, near-term NRE, product orders, and late-stage customer forecasts. Above 20-30%, the implied committed revenue starts looking too large versus what they actually disclose. Hence my practical estimate: 12-20%, with ~15% as the center.

The next Sivers term we need to discuss is NRE.

NRE means Non-Recurring Engineering Revenue. This is customer-funded R&D. The customer pays you to do R&D, and you book revenue. That’s basically what they do to get ciphers to customize their IP to the customer’s needs.

Now, most of their revenue is NRE, both wireless and photonics. That means they’re pretty much a startup at this point. This isn’t product revenue, and it’s not sustainable. Honestly, this would be a bear point at a much lower valuation, but at a valuation this high, this doesn’t even matter. They’re essentially a very frothy VC startup at this point, so NRE or not, what actually matters is if the product revenue can 100x with some massive qualification. Who cares if the tiny revenue base isn’t sustainable? That’s not what is making it a multi-billion dollar company anyways.

The (Fabricated) Bull Case

The few individuals who pump this stock focus on two main things.

This picture expresses the first one.

Basically, “omg $SIVE is in conversation with Ayar, Poet, LightMatter, and Optical Startup #463 and the ex-director-of-shits-and-giggles of one of these startups once had dinner with Matt Garman’s guinea pig, which means that they are supplying lasers to every single hyperscaler. $SIVE to the fucking moon”

This is completely and utterly wrong because, as I talked about before in the backlog section, conversations don’t mean shit without qualification and production orders. It’s not the hard part. It’s not what’s valuable. I don’t give a shit who supplies what to whom. If the product is uncompetitive, the buyer will find another supplier. If you have no customers, build a great product and the customers will come. What’s valuable is having a good product that passes qualification and performs well and then having the manufacturing expertise to ramp it at high yields and high gross margins. I can write a cold email and say I’m in conversations with Ayar Labs tomorrow if I wanted to. And not only that, the architecture of that startup has to actually be viable too (looking at you POET why do you even think you can beat hybrid bonding).

The second is possibly worse, which is that Sivers is a “chokepoint” or “bottleneck.”

(And no, a chokepoint is not different from a bottleneck. They’re the same thing.)

Sivers is literally the opposite of a bottleneck. They’re a fabless startup that people are calling a bottleneck.

Sivers hasn’t qualified anywhere. They are not choking off anyone. It’s like saying that the bottleneck for AI inference is Cerebras (lmfao). To find the real bottleneck for inference, you must look at who has majority share (Nvidia), then who owns the hard assets behind that majority share (memory and TSMC N3). The equivalent for optics here is Lumentum and AXTI.

A bottleneck must have both hard physical assets and substantial majority market share. Sivers has neither.

Why Is Sivers Fabless?

Today, Sivers is a fabless company. They have a facility in Glasgow which produces pilot volumes for R&D purposes, but in order to scale up to production volumes, they have WIN Semi as their contract manufacturer.

However, it wasn’t always this way. Turns out that in the past, Glasgow was pitched as a fab that could do up to $150 million in revenue. Yes, that is something around ten times their current photonics revenue base. It was only around the end of 2024 to the beginning of 2025 where this changed.

What happened? My best guess is yield.

Making lasers is really fucking hard. InP is brittle. Aixtron’s management said that Lumentum is their best customer in terms of their ability to use MOCVD machines to make lasers and even the best player out there only achieves 50% yields (on EML). That means one in every two dies is binned!

Manufacturing is brutal. Manufacturing is the moat, and that moat is what kept Sivers out of making their own lasers. That means that what they have left, which is just design IP, is a lot less valuable.

There is No Moat

Technology analysis will always be superior to supply chain analysis.

Here’s where I want to introduce you to a surprise. Sivers has no moat. Turns out that Lumentum also makes these laser arrays, and in fact Lumentum’s specs are even better, offering up to 100 mW per channel at 50°C, way higher than Sivers’ 65 mW per channel (with unspecified temperature).

As in classic Lumentum style, they also disclose way more other specs like spacing uniformity, channel power deviation, and reliability results. They literally do it better in every way.

This leads us to two main conclusions:

1. Laser arrays are not proprietary to Sivers. They don’t have a moat here that makes them better at making this specific technology.

2. Regular ultra-high power 400 mW lasers that send one powerful beam of light and split it, instead of using WDM and an array of lasers, are the superior default architecture.

The Wrong Architecture

Let’s zero in on the second one a bit further.

Lasers for CPO must also be placed far away from the optical engine.

Because this laser is so far away, in order for the light to reach the optical engine, it needs to survive a lot of coupling loss meaning that the light gets much less powerful every time it has to go through fiber and whatnot.

There are two ways to feed light into a CPO system.

The first is the ultra-high-power approach. You start with one very powerful continuous-wave laser outside the optical engine. That light enters the CPO package, survives the coupling loss, and then gets split into multiple lanes. This is the Lumentum-style architecture. The whole point is simple: start with so much clean light that even after losses and splitting, each lane still has enough photons to carry data.

The second approach is WDM, or wavelength division multiplexing. WDM just means using different colors of light. Instead of one very powerful laser, you use a laser array: many small lasers on one chip, each at a different wavelength. One color carries one data stream, another color carries another data stream, and so on. This is what Sivers is pitching.

WDM is a real and useful optical technique. But it solves the wrong problem for our beloved CPO application.

WDM solves a bandwidth density problem. It lets you push more data through fewer paths by stacking multiple colors together (and each data stream is one color).

UHP solves a more important problem: giving you way more starting photons.

CPO does not care about multiple colors. It fails if the light is too weak by the time it reaches the optical engine. Every connector, fiber attach, splitter, coupler, and waveguide eats optical power. If the source starts weak, adding more colors does not fix that. You just have many weak colors instead of one usable color.

In addition, Lumentum’s regular UHP architecture does not need WDM to push enough data. It can scale bandwidth through spatial parallelism: more lanes, more fibers, more waveguides, more parallel optical paths. That may be less elegant than WDM on paper, but it focuses on the one thing customers actually need first: actually having photons per lane after all that coupling loss.

WDM adds its own complexity. You need wavelength locking, thermal control, filters, tighter testing, more channel matching, and more ways for one bad channel to ruin the package. In CPO, the binding constraint appears to be optical power, reliability, and qualification.

So the conclusion is very clear!

Use many smaller lasers with different colors < < < Use much stronger lasers and split the light.

And this isn’t a Lumentum vs. Sivers thing where Lumentum wins the market with their architecture. It is that Lumentum has both architectures. They’re the leader in ultra-high power CW, and they’re also the leader in WDM laser arrays, but look at what they chose to ramp for production volume. What is their Greensboro fab going to churn out? UHP CW lasers!

Sivers is in the right market, but it is targeting the wrong architecture. Laser arrays may be useful in R&D programs, lower-loss systems, or niche WDM architectures, but the default CPO production ramp is being built around ultra-high-power external light. That is where the volume is.

Conclusion

Let’s recap. Sivers used to be an undiscovered small cap with a respectable thesis, but after a 20x return facilitated by large social media accounts (unethically and illegally) promoting the ticker, the valuation has gotten absurd. The only way to save the stock is through its optical division gaining a foothold in the CPO market, which is much less likely than what the cult is hoping for.

The cult believes Sivers will gain a foothold because they are in conversations or have remote connections to hyperscalers through various optical startups. This is wrong because what actually matters is its technology, and it is precisely technology where Sivers falls apart.

Sivers is fabless because they lack the manufacturing expertise in the very difficult process of indium phosphide fabrication. Which means they lack a moat, as they are skipping the hard part to do the easy part.

Sivers owns no exclusive technology, as Lumentum makes the same exact laser arrays, but better.

And finally, but most importantly, Sivers is targeting the wrong architecture entirely. Lumentum has a choice between UHP and WDM, and they made a choice to ramp the exact thing that is the opposite of what Sivers is doing, for volume production.

Sivers Semiconductor is the most overvalued stock in optics.

The last of my “big 5” (LITE, AIXA, INTC, BE) I haven’t started to super-intensely cover. But it was one of the first ever chip companies that I discovered and invested in!

It’s also up 10% today and 200%+ YTD and I’ve only ever added. I am proud of this one.

By accessing this content, you acknowledge and agree to our terms and conditions. This research is not financial advice.

The thesis here is 90% memory go brrr so it’s kind of not an idiosyncratic thing at all. SK hynix is only my favorite memory maker by a margin, but own Samsung and Micron, and really you should have the same result. Honestly, I don’t think it matters, because if once you’ve picked your memory maker and it starts going up, the cost of switching to another memory maker and paying taxes is probably going to be greater than whatever marginal benefit the other one has. This is basically to say that my largest position isn’t exactly a company, but a memory.

Although, if you look at my portfolio, memory isn’t my largest thematic exposure. Lumentum and Aixtron both contribute to optics, and that would then make up nearly 30% of my portfolio, so my favorite theme is still optics. But memory go brrr.

Contents

1. Supply vs. Demand

2. Book vs. Earnings

3. DRAM vs. NAND

4. Samsung vs. Micron vs. SK hynix

Supply vs. Demand

The point I’m about to make requires you to notice a visual quirk in any memory supply-demand graph from the sell-side or wherever.

Notice anything? The gap is small!

We are in perhaps the greatest memory shortage of all time ever in the universe, and DRAM is only about 5% behind demand, while NAND supply is about 4% behind demand. Those are not large absolute numbers.

If you’ve been in the weeds of memory, maybe take a step back and think about some other subsectors of AI infra, like optics, where Lumentum regularly says that they are 30% behind demand for their EML lasers and even more for scale across components.

However, very unintuitively, the words I just typed above are the most bullish sentences that you have ever read about memory.

The supply-demand gap is small. Yet, ASPs look like this.